Abstract: An improvement to an arbitration circuit in a dual port memory circuit device is disclosed. The arbitration circuit resolves near simultaneous identical address requests on the two ports. The arbitration circuit has a first state where the identical address request is resolved by permitting address requests to the first address port and denying writing of data to the second port and a second state where the identical address request is resolved by permitting address requests to the second address port and denying writing of data to the first port. The arbitration circuit also has a meta-state where the arbitration circuit is unable to resolve the identical address request. The improvement of the present invention detects the arbitration circuit in the meta-state and forcing the arbitration circuit into the first state in response to the detection of the meta-state.

Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Abstract: A dynamic MOS random-access memory is described which includes a circuit for permitting checking of the on chip refresh counter. The memory also includes a refresh generator, the frequency of which automatically varies to compensate for temperature variations. Other innovations include an arbitration circuit, a hidden refresh function and unique accessing of redundant lines.

Abstract: A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

Abstract: A random access read/write MOS memory device employs bistable latch or buffer circuits as the address inputs, data inputs, and the like. The buffers function to latch the data or address to allow the inputs to change states. The buffer is activated by TTL level inputs, exhibits low capacitance at its input, and switches states fast enough to allow rapid multiplexing of the addresses. Noise immunity is improved by selective implants of some of the transistors, and by use of filter capacitors connected between input nodes and Vss rather than Vdd.

Abstract: A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay, a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides precise control of the delay over a wide range. Power dissipation is reduced in the driver circuit by avoiding the possibility of d.c. current paths when the reset clock goes high.

Abstract: A clock generator for producing internal waveforms for an MOS dynamic RAM or the like provides a preselected delay period between input and output clocks. A pair-delay circuit including two transistor stages produces the desired delay; a driver circuit provides the necessary high level output. A pair of series transistors in the output of the pair-delay, with the node between the series transistors being precharged, provides a more precise control of the delay over a wide range, and the waveshape of the input to the driver is improved.