Patents by Inventor Edmund Au

Edmund Au has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8638796
    Abstract: A method and network device for re-ordering segments of a segmented data stream. The method includes receiving at least two segments of a segmented data stream. A descriptor for each of the at least two segments is obtained, and the at least two segments are re-ordered to generate re-ordered segments, where the re-ordered segments are in an original order. A set of re-ordered segments are processed to obtain at least one data packet, where at least one descriptor is utilized in the processing of the set of re-ordered segments.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: January 28, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Yie-Fong Dan, Edmund Au, Raymond Ng, Yanyan Cui
  • Publication number: 20100046519
    Abstract: A method and network device for re-ordering segments of a segmented data stream. The method includes receiving at least two segments of a segmented data stream. A descriptor for each of the at least two segments is obtained, and the at least two segments are re-ordered to generate re-ordered segments, where the re-ordered segments are in an original order. A set of re-ordered segments are processed to obtain at least one data packet, where at least one descriptor is utilized in the processing of the set of re-ordered segments.
    Type: Application
    Filed: August 22, 2008
    Publication date: February 25, 2010
    Applicant: CISCO TECHNOLOGY, INC.
    Inventors: Yie-Fong Dan, Edmund Au, Raymond Ng, Yanyan Cui
  • Patent number: 6360310
    Abstract: When a processing unit clock cycle period decreases (i.e., the processing unit operating frequency increases) such that the processing unit has only sufficient time to transfer accurately instruction fields from the instruction cache unit, the processing unit does not have sufficient time to determine the address of the next instruction to be retrieved from the instruction cache unit. In order to provide instruction fields to a pipelined processing unit with few breaks in the instruction field stream, the field in the program counter is incremented during to provide a speculative address of a next instruction field during a first clock cycle. During the first clock cycle, the instruction field identified by program counter field is accessed and transferred to the processor. The instruction field helps to determine an actual address of the next instruction field.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: March 19, 2002
    Assignee: NEC Electronics, Inc.
    Inventor: Edmund Au