Abstract: The techniques and systems described herein implement direct memory access in association with a wireless data transfer. In one example, data units are received at a device and it is determined that the data units have been transferred using low-power consumption data transfer and that the data units are to be directly stored in a predetermined memory (e.g., a dedicated memory) of the device. In another example, a first device provides an instruction to a partner device to store data in specific storage location(s) so that the data can be retrieved from the specific storage location(s) without interrupting a main processor of the partner device. The data may also be directly stored in the predetermined memory of the first device without interrupting a main processor of the first device.

Abstract: Application code is analyzed to determine if a hardware library could accelerate its execution. In particular, application code can be analyzed to identify calls to application programming interfaces (APIs) or other functions that have a hardware library implementation. The code can be analyzed to identify the frequency of such calls. Information from the hardware library can indicate characteristics of the library, such as its size, power consumption and FPGA resource usage. Information about the execution pattern of the application code also can be useful. This information, along with information about other concurrent processes using the FPGA resources, can be used to select a hardware library to implement functions called in the application code.

Abstract: Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are isolated to protect the FPGA and data transferred between the FPGA and other components of the computer system. For example, data written by the FPGA to memory is encrypted, and is decrypted within the FPGA when read back from memory. Data transferred between the FPGA and other components such as the CPU or GPU, whether directly or through memory, can similarly be encrypted using cryptographic keys known to the communicating components. Transferred data also can be digitally signed by the FPGA or other component to provide authentication. Code for programming the FPGA can be encrypted and signed by the author, loaded into the FPGA in an encrypted state, and then decrypted and authenticated by the FPGA itself, before programming the FPGA with the code.

Abstract: A metadata server configured to maintain storage assignment mappings in non-persistent storage is described herein. The tract storage assignment mappings associate servers with storage assignments, the storage assignments representing the data stored on the servers. Responsive to a failure, the metadata server receives the storage assignments from the servers and rebuilds the storage assignment mappings from the storage assignments. The metadata server is also configured to enable clients to operate during a recovery process for a failed server by providing the storage assignment mappings to the clients during the recovery process. Also during the recovery process, the replacement server for the failed server conditionally overwrites stored data with other data received from other servers as part of the recovery process.

Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Abstract: A plurality of servers configured to receive a plurality of requests associated with a plurality of byte sequences are described herein. The requests for each byte sequence are received by a single one of the servers. Each server is further configured to serially process the requests it receives while the other servers also perform serial processing of requests in parallel with the server. Also, the requests for each byte sequence are transmitted to the single one of the servers by a plurality of clients, each client independently identifying the single one of the servers for the byte sequence based on system metadata.

Abstract: Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.

Abstract: While connected to cloud storage, a computing device writes data and metadata to the cloud storage, indicates success of the write to an application of the computing device, and, after indicating success to the application, writes the data and metadata to local storage of the computing device. The data and metadata may be written to different areas of the local storage. The computing device may also determine that it has recovered from a crash or has connected to the cloud storage after operating disconnected and reconcile the local storage with the cloud storage. The reconciliation may be based at least on a comparison of the metadata stored in the area of the local storage with metadata received from the cloud storage. The cloud storage may store each item of data contiguously with its metadata as an expanded block.

Abstract: Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are isolated to protect the FPGA and data transferred between the FPGA and other components of the computer system. Transferred data can be digitally signed by the FPGA or other component to provide authentication. Code for programming the FPGA can be encrypted and signed by the author, loaded into the FPGA in an encrypted state, and then decrypted and authenticated by the FPGA itself, before programming the FPGA with the code. This code can be used to change the cryptographic operations performed in the FPGA, including keys, or decryption and encryption algorithms, or both.

Abstract: An illustrative operating system distributes two or more instances of the operating system over heterogeneous platforms of a computing device. The instances of the operating system work together to provide single-kernel semantics to present a common operating system abstraction to application modules. The heterogeneous platforms may include co-processors that use different instruction set architectures and/or functionality, different NUMA domains, etc. Further, the operating system allows application modules to transparently access components using a local communication path and a remote communication path. Further, the operating system includes a policy manager module that determines the placement of components based on affinity values associated with interaction relations between components. The affinity values express the sensitivity of the interaction relations to a relative location of the components.

Abstract: An illustrative operating system distributes two or more instances of the operating system over heterogeneous platforms of a computing device. The instances of the operating system work together to provide single-kernel semantics to present a common operating system abstraction to application modules. The heterogeneous platforms may include co-processors that use different instruction set architectures and/or functionality, different NUMA domains, etc. Further, the operating system allows application modules to transparently access components using a local communication path and a remote communication path. Further, the operating system includes a policy manager module that determines the placement of components based on affinity values associated with interaction relations between components. The affinity values express the sensitivity of the interaction relations to a relative location of the components.

Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.

Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Abstract: Implementations of a file system that is supported by a non-volatile memory that is directly connected to a memory bus, and placed side by side with a dynamic random access memory (DRAM), are described.

Abstract: Application code is analyzed to determine if a hardware library could accelerate its execution. In particular, application code can be analyzed to identify calls to application programming interfaces (APIs) or other functions that have a hardware library implementation. The code can be analyzed to identify the frequency of such calls. Information from the hardware library can indicate characteristics of the library, such as its size, power consumption and FPGA resource usage. Information about the execution pattern of the application code also can be useful. This information, along with information about other concurrent processes using the FPGA resources, can be used to select a hardware library to implement functions called in the application code.

Abstract: Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are isolated to protect the FPGA and data transferred between the FPGA and other components of the computer system. For example, data written by the FPGA to memory is encrypted, and is decrypted within the FPGA when read back from memory. Data transferred between the FPGA and other components such as the CPU or GPU, whether directly or through memory, can similarly be encrypted using cryptographic keys known to the communicating components. Transferred data also can be digitally signed by the FPGA or other component to provide authentication. Code for programming the FPGA can be encrypted and signed by the author, loaded into the FPGA in an encrypted state, and then decrypted and authenticated by the FPGA itself, before programming the FPGA with the code.

Abstract: Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. Components of an FPGA are isolated to protect the FPGA and data transferred between the FPGA and other components of the computer system. Transferred data can be digitally signed by the FPGA or other component to provide authentication. Code for programming the FPGA can be encrypted and signed by the author, loaded into the FPGA in an encrypted state, and then decrypted and authenticated by the FPGA itself, before programming the FPGA with the code. This code can be used to change the cryptographic operations performed in the FPGA, including keys, or decryption and encryption algorithms, or both.

Abstract: Field programmable gate arrays can be used as a shared programmable co-processor resource in a general purpose computing system. An FPGA can be programmed to perform functions, which in turn can be associated with one or more processes. With multiple processes, the FPGA can be shared, and a process is assigned to at least one portion of the FPGA during a time slot in which to access the FPGA. Programs written in a hardware description language for programming the FPGA are made available as a hardware library. The operating system manages allocating the FPGA resources to processes, programming the FPGA in accordance with the functions to be performed by the processes using the FPGA, and scheduling use of the FPGA by these processes.