Abstract: A method of controlling oxygen vacancy concentration in a semiconducting metal oxide includes exposing a treated surface of a crystalline metal oxide to water at a temperature and pressure sufficient to maintain the water in a liquid phase. During the exposure, a portion of the water is adsorbed onto the treated surface and dissociates into atomic oxygen and hydrogen. The atomic oxygen is injected into and diffuses through the crystalline metal oxide, forming isolated oxygen interstitials and oxygen defect complexes. The isolated oxygen interstitials replace oxygen vacancies in the crystalline metal oxide.

Abstract: A composition comprising an engineered defect concentration comprises a metal oxide single crystal having a polar surface and a bulk concentration of interstitial oxygen (Oi) of at least about 1014 atoms/cm3. The polar surface comprises a concentration of impurity species of about 5% or less of a monolayer. A method of engineering a defect concentration in a single crystal comprises exposing a metal oxide single crystal having a polar surface to molecular oxygen at a temperature of about 850° C. or less, and injecting atomic oxygen into the single crystal at an effective diffusion rate Deff of at least about 10?16 cm2/s.

Abstract: A composition comprising an engineered defect concentration comprises a metal oxide single crystal having a polar surface and a bulk concentration of interstitial oxygen (Oi) of at least about 1014 atoms/cm3. The polar surface comprises a concentration of impurity species of about 5% or less of a monolayer. A method of engineering a defect concentration in a single crystal comprises exposing a metal oxide single crystal having a polar surface to molecular oxygen at a temperature of about 850° C. or less, and injecting atomic oxygen into the single crystal at an effective diffusion rate Deff of at least about 10?16 cm2/s.

Abstract: The present invention provides methods for controlling defects in materials, including point defects, such as interstitials and vacancies, and extended defects, including dislocations and clusters. Defect control provided by the present invention allows for fabrication and processing of materials and/or structures having a selected abundance, spatial distribution and/or concentration depth profile of one or more types of defects in a material, such as vacancies and/or interstitials in a crystalline material. Methods of the invention are useful for processing materials by controlling defects to access beneficial physical, optical, chemical and/or electronic properties.

Abstract: The present invention provides methods for controlling defects in materials, including point defects, such as interstitials and vacancies, and extended defects, including dislocations and clusters. Defect control provided by the present invention allows for fabrication and processing of materials and/or structures having a selected abundance, spatial distribution and/or concentration depth profile of one or more types of defects in a material, such as vacancies and/or interstitials in a crystalline material. Methods of the invention are useful for processing materials by controlling defects to access beneficial physical, optical, chemical and/or electronic properties.

Abstract: Described herein are processing conditions, techniques, and methods for preparation of ultra-shallow semiconductor junctions. Methods described herein utilize semiconductor surface processing or modification to limit the extent of dopant diffusion under annealing conditions (e.g. temperature ramp rates between 100 and 5000° C./second) previously thought impractical for the preparation of ultra-shallow semiconductor junctions. Also described herein are techniques for preparation of ultra-shallow semiconductor junctions utilizing the presence of a solid interface for control of dopant diffusion and activation.

Abstract: The present invention provides methods for fabricating semiconductor structures and devices, particularly ultra-shallow doped semiconductor structures exhibiting low electrical resistance. Methods of the present invention use modification of the composition of semiconductor surfaces to allow fabrication of a doped semiconductor structure having a selected dopant concentration depth profile, which provides useful junctions and other device components in microelectronic and nanoelectronic devices, such as transistors in high density integrated circuits. Surface modification in the present invention also allows for control of the concentration and depth profile of defects, such as interstitials and vacancies, in undersaturated semiconductor materials.

Abstract: Described herein are processing conditions, techniques, and methods for preparation of ultra-shallow semiconductor junctions. Methods described herein utilize semiconductor surface processing or modification to limit the extent of dopant diffusion under annealing conditions (e.g. temperature ramp rates between 100 and 5000° C./second) previously thought impractical for the preparation of ultra-shallow semiconductor junctions. Also described herein are techniques for preparation of ultra-shallow semiconductor junctions utilizing the presence of a solid interface for control of dopant diffusion and activation.

Abstract: The present invention concerns a completely selective and efficient method for chemical vapor deposition of titanium disilicide onto silicon regions of a silicon substrate including silicon dioxide regions. According to the method of the present invention a silicon substrate is heated to a low temperature. Silicon nucleation is induced by the introduction of a silicon precursor, such as silane. Silicon nucleates primarily on the silicon regions, with minimal nucleation on silicon dioxide regions. The silicon nuclei are then converted to titanium disilicide by the low pressure introduction of titanium tetrachloride with or without continued supply of silane. Etching, preferably using chlorine gas, is used to remove the titanium disilicide formed from conversion. The etching leaves the silicon dioxide regions completely intact, while the silicon region is slightly textured.