Patents by Inventor Edmund J. Gieske
Edmund J. Gieske has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240036762Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.Type: ApplicationFiled: July 27, 2023Publication date: February 1, 2024Inventors: Edmund J. Gieske, Cagdas Dirik, Elliott C. Cooper-Balis, Robert M. Walker, Amitava Majumdar, Sujeet Ayyapureddi, Yang Lu, Ameen D. Akel, Niccolò Izzo, Danilo Caraccio, Markus H. Geiger
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Publication number: 20240038291Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.Type: ApplicationFiled: October 26, 2022Publication date: February 1, 2024Inventors: Edmund J. Gieske, Sujeet Ayyapureddi, Niccolò Izzo
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Publication number: 20230393770Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.Type: ApplicationFiled: September 16, 2022Publication date: December 7, 2023Inventors: Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis, Amitava Majumdar, Robert M. Walker, Danilo Caraccio
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Publication number: 20230395126Abstract: An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can include row hammer detection circuitry configured to receive signaling indicative of a row activation command having a row address, increment a row counter corresponding to the row address stored in a stored in a data structure in a register or storage device, determine whether the incremented row counter is greater than a row hammer threshold, and issue a row hammer mitigation command to mitigate row hammer.Type: ApplicationFiled: June 1, 2023Publication date: December 7, 2023Inventors: Edmund J. Gieske, Cagdas Dirik, Robert M. Walker
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Patent number: 11416257Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.Type: GrantFiled: April 10, 2019Date of Patent: August 16, 2022Assignee: International Business Machines CorporationInventors: Naga P. Gorti, Ehsan Fatehi, Nicholas R. Orzol, Christian Zoellin, Edmund J. Gieske
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Patent number: 10942743Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: GrantFiled: April 28, 2020Date of Patent: March 9, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Publication number: 20200326951Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.Type: ApplicationFiled: April 10, 2019Publication date: October 15, 2020Inventors: Naga P. GORTI, Ehsan FATEHI, Nicholas R. ORZOL, Christian ZOELLIN, Edmund J. GIESKE
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Publication number: 20200257535Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Patent number: 10725783Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: GrantFiled: November 2, 2018Date of Patent: July 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Publication number: 20200142702Abstract: According to one or more embodiments, an example computer-implemented method for executing one or more out-of-order instructions by a processing unit, includes decoding an instruction to be executed, and based on a determination that the instruction is a store instruction, identifying a split load-hit-store (LHS) table for the store instruction, wherein a LHS table of the processing unit includes multiple split LHS tables. Identifying the split LHS table includes determining, for the store instruction, a first split LHS table by performing a mod operation using one or more operands from the store instruction, and adding one or more parameters of the store instruction in the first split LHS table by generating an ITAG for the store instruction. The method further includes dispatching the store instruction for execution to an issue queue with the ITAG.Type: ApplicationFiled: November 2, 2018Publication date: May 7, 2020Inventors: Ehsan Fatehi, Richard J. Eickemeyer, Edmund J. Gieske
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Techniques for utilizing translation lookaside buffer entry numbers to improve processor performance
Patent number: 8984254Abstract: A technique for operating a processor includes translating, using an associated translation lookaside buffer, a first virtual address into a first physical address through a first entry number in the translation lookaside buffer. The technique also includes translating, using the translation lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.Type: GrantFiled: September 28, 2012Date of Patent: March 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Thang M. Tran, Edmund J. Gieske -
Techniques for Utilizing Transaction Lookaside Buffer Entry Numbers to Improve Processor Performance
Publication number: 20140095784Abstract: A technique for operating a processor includes translating, using an associated transaction lookaside buffer, a first virtual address into a first physical address through a first entry number in the transaction lookaside buffer. The technique also includes translating, using the transaction lookaside buffer, a second virtual address into a second physical address through a second entry number in the translation lookaside buffer. The technique further includes, in response to the first entry number being the same as the second entry number, determining that the first and second virtual addresses point to the same physical address in memory and reference the same data.Type: ApplicationFiled: September 28, 2012Publication date: April 3, 2014Inventors: Thang M. Tran, Edmund J. Gieske -
Patent number: 8677205Abstract: A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.Type: GrantFiled: March 10, 2011Date of Patent: March 18, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Ravindraraj Ramaraju, Edmund J. Gieske, David F. Greenberg
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Patent number: 8458447Abstract: A data processor includes a branch target buffer (BTB) having a plurality of BTB entries grouped in ways. The BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address.Type: GrantFiled: June 17, 2011Date of Patent: June 4, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Thang M. Tran, Edmund J. Gieske, Michael B. Schinzler
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Publication number: 20120324209Abstract: A data processor includes a branch target buffer (BTB) having a plurality of BTB entries grouped in ways. The BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address.Type: ApplicationFiled: June 17, 2011Publication date: December 20, 2012Inventors: Thang M. Tran, Edmund J. Gieske, Michael B. Schinzler
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Publication number: 20120233498Abstract: A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.Type: ApplicationFiled: March 10, 2011Publication date: September 13, 2012Inventors: Ravindraraj Ramaraju, Edmund J. Gieske, David F. Greenberg