Patents by Inventor Edmund Kenneth Banghart
Edmund Kenneth Banghart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210091222Abstract: A FinFET device is provided, which includes a semiconductor substrate, a fin structure and a dielectric material. The fin structure is extending from the semiconductor substrate, the fin structure having an upper fin section, a middle fin section and a lower fin section. The dielectric material is over the semiconductor substrate embedding a first portion of the lower fin section. The dielectric material forms shallow trench isolation regions of the FinFET device.Type: ApplicationFiled: September 24, 2019Publication date: March 25, 2021Inventors: TAO CHU, BINGWU LIU, ANTON VADIMOVICH TOKRANOV, WEI MA, EDMUND KENNETH BANGHART, GEORGE ROBERT MULFINGER, TYLER JAMES SHERWOOD
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Patent number: 10347740Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.Type: GrantFiled: December 2, 2016Date of Patent: July 9, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Xusheng Wu, Min-hwa Chi, Edmund Kenneth Banghart
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Publication number: 20170222054Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.Type: ApplicationFiled: April 19, 2017Publication date: August 3, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Edmund Kenneth BANGHART, Mitsuhiro TOGO, Shesh Mani PANDEY
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Patent number: 9679990Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.Type: GrantFiled: August 8, 2014Date of Patent: June 13, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Edmund Kenneth Banghart, Mitsuhiro Togo, Shesh Mani Pandey
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Publication number: 20170084718Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.Type: ApplicationFiled: December 2, 2016Publication date: March 23, 2017Inventors: Xusheng WU, Min-hwa CHI, Edmund Kenneth BANGHART
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Patent number: 9583625Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.Type: GrantFiled: October 24, 2014Date of Patent: February 28, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Xusheng Wu, Min-hwa Chi, Edmund Kenneth Banghart
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Patent number: 9570291Abstract: Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.Type: GrantFiled: July 14, 2015Date of Patent: February 14, 2017Assignee: GLOBALFOUNDRIES, INC.Inventors: Shishir Ray, Sandeep Gaan, Sheldon Meyers, Nisha Pillai, Edmund Kenneth Banghart, Kyle Jung
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Publication number: 20170018426Abstract: Semiconductor substrates and methods for fabricating integrated circuits are provided. A method for fabricating an integrated circuit includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.Type: ApplicationFiled: July 14, 2015Publication date: January 19, 2017Inventors: Shishir Ray, Sandeep Gaan, Sheldon Meyers, Nisha Pillai, Edmund Kenneth Banghart, Kyle Jung
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Publication number: 20160118500Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.Type: ApplicationFiled: October 24, 2014Publication date: April 28, 2016Inventors: Xusheng WU, Min-hwa CHI, Edmund Kenneth BANGHART
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Publication number: 20160043190Abstract: Semiconductor structures and methods of fabrication are provided, with one or both of an extended source-to-channel interface or an extended drain-to-channel interface. The fabrication method includes, for instance, recessing a semiconductor material to form a cavity adjacent to a channel region of a semiconductor structure being fabricated, the recessing forming a first cavity surface and a second cavity surface within the cavity; and implanting one or more dopants into the semiconductor material through the first cavity surface to define an implanted region within the semiconductor material, and form an extended channel interface, the extended channel interface including, in part, an interface of the implanted region within the semiconductor material to the channel region of the semiconductor structure. In one embodiment, the semiconductor structure with the extended channel interface is a FinFET.Type: ApplicationFiled: August 8, 2014Publication date: February 11, 2016Applicant: GLOBALFOUNDRIES Inc.Inventors: Edmund Kenneth BANGHART, Mitsuhiro TOGO, Shesh Mani PANDEY
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Patent number: 9087860Abstract: Methods are provided for fabricating a fin-type field effect transistor(s), having a channel region within a fin. The methods include: establishing a protective material above an upper surface of the fin, and an isolation material adjacent to at least one sidewall of the fin, the isolation material being recessed down from the upper surface of the fin, for instance, for approximately a height of the channel region within the fin; and providing a punch-through stop dopant region within the fin below the channel region, the providing including implanting a punch-through stop dopant into the isolation material and laterally diffusing the punch-through stop dopant from the isolation material into the fin to form the punch-through stop region within the fin beneath the channel region.Type: GrantFiled: April 29, 2014Date of Patent: July 21, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Edmund Kenneth Banghart, Yanxiang Liu, Shesh Mani Pandey