Abstract: Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.

Abstract: Methods, systems, and apparatuses are described for the assembly of integrated circuit (IC) packages. A substrate panel is formed that includes a plurality of substrates. The substrate panel is singulated to separate the plurality of substrates. At least a subset of the separated substrates is attached to a surface of a carrier. One or more dies are attached to each of the substrates on the carrier. The dies and the substrates are encapsulated on the carrier with a molding compound. The carrier is detached from the encapsulated dies and substrates to form a molded assembly that includes the molding compound encapsulating the dies and substrates. A plurality of interconnects is attached to each of the substrates at a surface of the molded assembly. The molded assembly is singulated to form a plurality of IC packages. Each IC package includes at least one of the dies and a substrate.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.

Abstract: Methods, systems, and apparatuses are provided for integrated circuit packages and for enabling electrostatic discharge (ESD) testing of the same. A package includes an integrated circuit chip, a substrate, a first electrically conductive trace, and a second electrically conductive trace. The substrate includes a first electrically conductive region and a second electrically conductive region. The first region is coupled to a first ground signal of the chip, and the second region is coupled to a second ground signal of the chip. The first trace is coupled to the first region and the second trace is coupled to the second region. A portion of the first trace is proximate to a portion of the second trace. An electrically conductive material may be deposited to electrically couple the first and second traces to enable ESD protection testing of the package.

Abstract: Methods, systems, and apparatuses are provided for integrated circuit packages and for enabling electrostatic discharge (ESD) testing of the same. A package includes an integrated circuit chip, a substrate, a first electrically conductive trace, and a second electrically conductive trace. The substrate includes a first electrically conductive region and a second electrically conductive region. The first region is coupled to a first ground signal of the chip, and the second region is coupled to a second ground signal of the chip. The first trace is coupled to the first region and the second trace is coupled to the second region. A portion of the first trace is proximate to a portion of the second trace. An electrically conductive material may be deposited to electrically couple the first and second traces to enable ESD protection testing of the package.

Abstract: Provided is a method and system for designing an integrated circuit (IC) substrate, the substrate being formed to include at least one die. The method includes providing at least portions of IC power and a grounding function on a metal 2 substrate layer and utilizing all of a metal 3 substrate layer for the grounding function. Portions of the metal 2 layer and a metal 4 layer are utilized for the IC power, wherein all of the IC power is centralized underneath the die.