Patents by Inventor Edmund M. Sikorski
Edmund M. Sikorski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9711365Abstract: Pretreatment of an etch chamber for performing a silicon etch process and Bosch process can be effected by running a deposition process employing C5HF7, or by running an alternating deposition and etch process employing C5H2F6 and SF6. It has been discovered that the pretreatment of the etch chamber for the silicon etch process can enhance the etch rate of silicon by at least 50% without adverse effect on etch profile during a first each process following the pretreatment, while the etch rate enhancement factor decreases over time. By periodically performing the pretreatment in the etch chamber, the throughput of the etch chamber can be increased without adversely impacting the etch profile of the processed substrates.Type: GrantFiled: May 2, 2014Date of Patent: July 18, 2017Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, ZEON CORPORATIONInventors: Eric A. Joseph, Goh Matsuura, Masahiro Nakamura, Edmund M. Sikorski, Bang N. To
-
Publication number: 20150318182Abstract: Pretreatment of an etch chamber for performing a silicon etch process and Bosch process can be effected by running a deposition process employing C5HF7, or by running an alternating deposition and etch process employing C5H2F6 and SF6. It has been discovered that the pretreatment of the etch chamber for the silicon etch process can enhance the etch rate of silicon by at least 50% without adverse effect on etch profile during a first each process following the pretreatment, while the etch rate enhancement factor decreases over time. By periodically performing the pretreatment in the etch chamber, the throughput of the etch chamber can be increased without adversely impacting the etch profile of the processed substrates.Type: ApplicationFiled: May 2, 2014Publication date: November 5, 2015Applicants: ZEON Corporation, International Business Machines CorporationInventors: Eric A. Joseph, Goh Matsuura, Masahiro Nakamura, Edmund M. Sikorski, Bang N. To
-
Patent number: 8928124Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.Type: GrantFiled: August 13, 2013Date of Patent: January 6, 2015Assignees: International Business Machines Corporation, ZEON CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura
-
Patent number: 8652969Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.Type: GrantFiled: October 26, 2011Date of Patent: February 18, 2014Assignees: International Business Machines Corporation, ZEON CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura
-
Publication number: 20130328173Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.Type: ApplicationFiled: August 13, 2013Publication date: December 12, 2013Applicants: ZEON Corporation, International Business Machines CorporationInventors: Nicholas C. M. Fuller, Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura
-
Publication number: 20130105947Abstract: A hydrofluorocarbon gas is employed as a polymer deposition gas in an anisotropic etch process employing an alternation of an etchant gas and the polymer deposition gas to etch a deep trench in a semiconductor substrate. The hydrofluorocarbon gas can generate a thick carbon-rich and hydrogen-containing polymer on sidewalls of a trench at a thickness on par with the thickness of the polymer on a top surface of the semiconductor substrate. The thick carbon-rich and hydrogen-containing polymer protects sidewalls of a trench, thereby minimizing an undercut below a hard mask without degradation of the overall rate. In some embodiments, an improvement in the overall etch rate can be achieved.Type: ApplicationFiled: October 26, 2011Publication date: May 2, 2013Applicants: ZEON CORPORATION, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicholas C. M. Fuller, Eric A. Joseph, Edmund M. Sikorski, Goh Matsuura
-
Patent number: 7820552Abstract: An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.Type: GrantFiled: March 13, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: Siva Kanakasabapathy, Ying Zhang, Edmund M. Sikorski, Hongwen Yan, Vijay Narayanan, Vamsi K. Paruchuri, Bruce B. Doris
-
Publication number: 20080224238Abstract: An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.Type: ApplicationFiled: March 13, 2007Publication date: September 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Siva Kanakasabapathy, Ying Zhang, Edmund M. Sikorski, Hongwen Yan, Vijay Narayanan, Vamsi K. Paruchuri, Bruce B. Doris
-
Patent number: 6743686Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.Type: GrantFiled: June 14, 2002Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Kam Leung Lee, Ying Zhang, Maheswaran Surendra, Edmund M. Sikorski
-
Patent number: 6518136Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.Type: GrantFiled: December 14, 2000Date of Patent: February 11, 2003Assignee: International Business Machines CorporationInventors: Kam Leung Lee, Ying Zhang, Maheswaran Surendra, Edmund M. Sikorski
-
Publication number: 20020151145Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.Type: ApplicationFiled: June 14, 2002Publication date: October 17, 2002Applicant: Reel/FrameInventors: Kam Leung Lee, Ying Zhang, Maheswaran Surendra, Edmund M. Sikorski
-
Publication number: 20020076889Abstract: A process for making abrupt, e.g. <20 nm/decade, PN junctions and haloes in, e.g., CMOSFETs having gate lengths of, e.g. <50 nm, uses a mask, e.g., sidewall spacers, during ion implantation of gate, source, and drain regions. The mask is removed after source-drain activation by annealing and source and drain extension regions are then implanted. Then the extension regions are activated. Thereafter halo regions are implanted and activated preferably using spike annealing to prevent their diffusion. The process can also be used to make diodes, bipolar transistors, etc. The activation annealing steps can be combined into a single step near the end of the process.Type: ApplicationFiled: December 14, 2000Publication date: June 20, 2002Inventors: Kam Leung Lee, Ying Zhang, Maheswaran Surendra, Edmund M. Sikorski