Patents by Inventor Edmund R. Brown

Edmund R. Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Cloud-based diagnostics and remediation
    Patent number: 9449278
    Abstract: Troubleshooting a technical problem on a user device using a network-based remediation platform. Receiving problem statements relating to technical problems associated with a user device, activating a domain of cases, assigning a score for the cases based on a scoring algorithm, and determining one or more remediation actions to suggest based on the score.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: September 20, 2016
    Assignee: Apple Inc.
    Inventors: Efstratios N. Davlos, Francimar C. Schmitt, Edmund R. Brown, Gavin Anthony Condon
  • CLOUD-BASED DIAGNOSTICS AND REMEDIATION
    Publication number: 20140310222
    Abstract: Troubleshooting a technical problem on a user device using a network-based remediation platform. Receiving problem statements relating to technical problems associated with a user device, activating a domain of cases, assigning a score for the cases based on a scoring algorithm, and determining one or more remediation actions to suggest based on the score.
    Type: Application
    Filed: August 2, 2013
    Publication date: October 16, 2014
    Applicant: Apple Inc.
    Inventors: Efstratios N. Davlos, Francimar C. Schmitt, Edmund R. Brown, Gavin Anthony Condon
  • Pseudo-random binary sequence generators
    Patent number: 4748576
    Abstract: A pseudo-random binary sequence generator comprises at least one shift register (S, T) arranged in a recirculating loop and having a plurality of logic gates (G) for logically combining the outputs of selected stages of the register to provide a pseudo-random sequence, and a multiplexer (M), having a p data inputs and q address inputs all connected to selected shift register stages, and which selects at any instant one of the p data input bits in accordance with the q-bit address word to provide the generator output. The number s of logic gates is especially high and is related to the total number r of shift register stages (r>p+q) by the expression: 2.sup.s .gtoreq.r.sup.2. Some of the shift register stages of the or each shift register are connected to selected data inputs of the multiplexer and others of the stages of the same shift register are connected to selected address inputs of the multiplexer.
    Type: Grant
    Filed: October 1, 1985
    Date of Patent: May 31, 1988
    Assignee: U.S. Philips Corporation
    Inventors: Henry J. Beker, Luc Emiel L. Boes, Peter R. Brennand, Edmund R. Brown, Gerald O. Crowther, Wilhelmus M. Dorn, Stanley M. Edwardson, Stephen R. Ely, Louis C. Guillou, Peter M. Jenner, Sylvia M. Jennings, Michael J. Knee, Arthur G. Mason, Jean-Marie C. Nicolas