Patents by Inventor Edmund Sales Cabatbat
Edmund Sales Cabatbat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087992Abstract: A chip package is provided. The chip package includes a first chip, a second chip, an electrically conductive structure to which the first chip and the second chip are mounted, at least one contact terminal for electrically contacting the first chip and/or the second chip, and encapsulation material at least partially encapsulating the first chip, the second chip, and the electrically conductive structure. The encapsulation material forms a chip package body from which the at least one contact terminal protrudes. At least a portion of the electrically conductive structure forms a portion of an outer surface of the chip package body.Type: ApplicationFiled: August 22, 2023Publication date: March 14, 2024Inventors: Ke Yan Tean, Edmund Sales Cabatbat, Kean Ming Koe
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Patent number: 11652078Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.Type: GrantFiled: April 20, 2021Date of Patent: May 16, 2023Assignee: Infineon Technologies AGInventors: Edmund Sales Cabatbat, Thai Kee Gan, Kean Ming Koe, Ke Yan Tean
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Publication number: 20220336401Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.Type: ApplicationFiled: April 20, 2021Publication date: October 20, 2022Inventors: Edmund Sales Cabatbat, Thai Kee Gan, Kean Ming Koe, Ke Yan Tean
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Patent number: 11417538Abstract: A semiconductor package includes a die pad, a die, a first lead, a plurality of second leads, and a mold material. The die is electrically coupled to the die pad. The first lead is electrically coupled to the die. The plurality of second leads are electrically coupled to the die. The plurality of second leads are adjacent to the first lead. The mold material encapsulates at least a portion of the die pad, the die, the first lead, and the plurality of second leads. Each of the plurality of second leads extends a farther distance from the mold material than the first lead.Type: GrantFiled: May 22, 2020Date of Patent: August 16, 2022Assignee: Infineon Technologies AGInventors: Thai Kee Gan, Edmund Sales Cabatbat
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Publication number: 20210366728Abstract: A semiconductor package includes a die pad, a die, a first lead, a plurality of second leads, and a mold material. The die is electrically coupled to the die pad. The first lead is electrically coupled to the die. The plurality of second leads are electrically coupled to the die. The plurality of second leads are adjacent to the first lead. The mold material encapsulates at least a portion of the die pad, the die, the first lead, and the plurality of second leads. Each of the plurality of second leads extends a farther distance from the mold material than the first lead.Type: ApplicationFiled: May 22, 2020Publication date: November 25, 2021Applicant: Infineon Technologies AGInventors: Thai Kee Gan, Edmund Sales Cabatbat
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Patent number: 10971436Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.Type: GrantFiled: June 13, 2019Date of Patent: April 6, 2021Assignee: Infineon Technologies AGInventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
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Patent number: 10840164Abstract: A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.Type: GrantFiled: May 18, 2018Date of Patent: November 17, 2020Assignee: Infineon Technologies AGInventors: Chii Shang Hong, Edmund Sales Cabatbat, Lee Shuang Wang
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Publication number: 20200020618Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.Type: ApplicationFiled: June 13, 2019Publication date: January 16, 2020Inventors: Thomas STOEK, Chii Shang HONG, Chiew Li TAI, Edmund Sales CABATBAT
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Publication number: 20190355643Abstract: A semiconductor device package includes an electrically conductive die pad having a die attach surface and an outer surface. A semiconductor die is mounted on the die attach surface. An encapsulant material encapsulates the semiconductor die and exposes the outer surface of the die pad. A first lead directly contacts the die pad, extends away from a first sidewall of the encapsulant material, and bends towards a lower side of the encapsulant material. A second lead is electrically connected to a terminal of the semiconductor die, extends away from a second sidewall of the encapsulant material, and bends towards the lower side of the encapsulant material. A first lateral section of the first lead that intersects the first sidewall is vertically offset from a second lateral section of the second lead that intersects the second sidewall.Type: ApplicationFiled: May 18, 2018Publication date: November 21, 2019Inventors: Chii Shang Hong, Edmund Sales Cabatbat, Lee Shuang Wang
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Patent number: 10354943Abstract: An example multi-branch terminal for an integrated circuit (IC) package is described herein. An example multi-branch terminal of an integrated circuit (IC), may include a first branch that may include an active bonding with a chip of the IC, wherein the active bonding may include a wire bonded to the chip of the IC; and a second branch that may include a passive bonding with the chip of the IC, wherein the passive bonding may include a capacitor bonded to the second branch and a first terminal of the IC.Type: GrantFiled: July 12, 2018Date of Patent: July 16, 2019Assignee: Infineon Technologies AGInventors: Thomas Stoek, Chii Shang Hong, Chiew Li Tai, Edmund Sales Cabatbat
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Patent number: 10083899Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.Type: GrantFiled: January 23, 2017Date of Patent: September 25, 2018Assignee: Infineon Technologies AGInventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
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Publication number: 20180211907Abstract: A method of forming a semiconductor device package includes providing a lead frame having a peripheral structure and a heat slug having an upper and lower surface, the heat slug being attached to the peripheral structure. A semiconductor die is attached to the heat slug. The semiconductor die is encapsulated with a molding compound while the heat slug is attached to the peripheral structure. The heat slug is completely devoid of fasteners before the encapsulating.Type: ApplicationFiled: January 23, 2017Publication date: July 26, 2018Inventors: Mohd Kahar Bajuri, Edmund Sales Cabatbat, Gaylord Evangelista Cruz, Amirul Afiq Hud, Teck Sim Lee, Norbert Joson Santos, Chiew Li Tai, Chin Wei Yang
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Patent number: 9048397Abstract: A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED.Type: GrantFiled: January 6, 2014Date of Patent: June 2, 2015Assignee: Carsem (M) SDN. BHD.Inventors: Edmund Sales Cabatbat, Lily Khor, Ho Tuck Ming
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Publication number: 20150087087Abstract: A method of disposing a phosphor material on an LED such that the LED emits white light and adjusting the quantity of phosphor material such that the white light meets a color target. A formulated procedure is used to determine the adjustment required, and includes a correlation between a change in position of a color of an LED on a CIE diagram and a known quantity of phosphor material added to the LED.Type: ApplicationFiled: January 6, 2014Publication date: March 26, 2015Applicant: CARSEM (M) SDN. BHD.Inventors: Edmund Sales Cabatbat, Lily Khor, Ho Tuck Ming