Patents by Inventor Edmund Sprogis
Edmund Sprogis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070029045Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.Type: ApplicationFiled: October 17, 2006Publication date: February 8, 2007Applicant: International Business Machines CorporationInventors: Timothy Krywanczyk, Edmund Sprogis
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Publication number: 20060273438Abstract: The present invention is directed to an integrated circuit module device. The device includes a first semiconductor chip having a first circuit layer and at least one first interconnection element disposed on a first chip surface. The at least one first interconnection element is electrically coupled to the first circuit layer. A second semiconductor chip includes a second circuit layer and at least one second interconnection element disposed on a second chip surface. The at least one second interconnection element is electrically coupled to the second circuit layer. The at least one first interconnection element is connected to the at least one second interconnection element to establish electrical continuity between the first circuit layer and the second circuit layer. The first surface is adjoined to the second surface. At least one ring delay circuit includes a first ring delay path partially disposed on the first circuit layer and a second ring delay path partially disposed on the second circuit layer.Type: ApplicationFiled: June 3, 2005Publication date: December 7, 2006Applicant: International Business Machines CorporationInventors: Brent Anderson, Edmund Sprogis
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Publication number: 20060246703Abstract: A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.Type: ApplicationFiled: April 27, 2005Publication date: November 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter, Edmund Sprogis
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Publication number: 20060152333Abstract: A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.Type: ApplicationFiled: January 10, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Douglas Coolbaugh, Ebenezer Eshun, Terence Hook, Robert Rassel, Edmund Sprogis, Anthony Stamper, William Murphy
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Publication number: 20060110905Abstract: A bond pad for effecting through-wafer connections to an integrated circuit or electronic package and method of producing thereof. The bond pad includes a high surface area aluminum bond pad in order to resultingly obtain a highly reliable, low resistance connection between bond pad and electrical leads.Type: ApplicationFiled: November 23, 2004Publication date: May 25, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Adkisson, Jeffrey Gambino, Mark Jaffe, Richard Rassel, Edmund Sprogis
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Publication number: 20060027934Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: October 3, 2005Publication date: February 9, 2006Inventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker, Yu-Ting Cheng, Kenneth Ocheltree, Robert Montoye
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Publication number: 20050227449Abstract: A method for manufacturing a self-compensating resistor within an integrated circuit is disclosed. The self-compensating resistor includes a first resistor and a second resistor. The first resistor having a first resistance value is initially formed, and then the second resistor having a second resistance value is subsequently formed. The second resistor is connected in series with the first resistor. The second resistance value is less than the first resistance value, but the total resistance value of the first and second resistors lies beyond a desired target resistance range. Finally, an electric current is sent to the second resistor to change the dimension of the second resistor such that the total resistance value of the first and second resistors falls within the desired target resistance range.Type: ApplicationFiled: April 8, 2004Publication date: October 13, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: William Murphy, Edmund Sprogis, Anthony Stamper, Erick Walton
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Patent number: 6949458Abstract: A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.Type: GrantFiled: February 10, 2003Date of Patent: September 27, 2005Assignee: International Business Machines CorporationInventors: Edward W. Conrad, Chung H. Lam, Dale W. Martin, Edmund Sprogis
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Publication number: 20050127500Abstract: In an integrated circuit packaging structure, such as in an MCM or in a SCM, a compliant thermally conductive material is applied between a heat-generating integrated circuit chip and a substrate attached thereto. Raised regions are defined on the back side of the chip aligned to areas of a higher than average power density on the front active surface of the chip such that a thinner layer of the compliant thermally conductive material is disposed between the chip and the substrate in this area after assembly thereof resulting in a reduced “hot-spot” temperature on the chip. In an exemplary embodiment, the substrate includes one of a heat sink, cooling plate, thermal spreader, heat pipe, thermal hat, package lid, or other cooling member.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Applicant: International Business Machines CorporationInventors: Evan Colgan, Claudis Feger, Gary Goth, George Katopis, John Magerlein, Edmund Sprogis
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Publication number: 20050121768Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.Type: ApplicationFiled: December 5, 2003Publication date: June 9, 2005Applicant: International Business Machines CorporationInventors: Daniel Edelstein, Paul Andry, Leena Buchwalter, Jon Casey, Sherif Goma, Raymond Horton, Gareth Hougham, Michael Lane, Xiao Liu, Chirag Patel, Edmund Sprogis, Michelle Steen, Brian Sundlof, Cornelia Tsang, George Walker
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Publication number: 20050106879Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.Type: ApplicationFiled: November 13, 2003Publication date: May 19, 2005Inventors: Timothy Krywanczyk, Edmund Sprogis
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Publication number: 20050106834Abstract: A method for filling vias, and in particular initially blind vias, in a wafer, and various apparatus for performing the method, comprising evacuating air from the vias; trapping at least a portion of the wafer and a paste for filling the vias between two surfaces; and pressurizing the paste to fill the vias.Type: ApplicationFiled: November 3, 2003Publication date: May 19, 2005Inventors: Paul Andry, Jon Casey, Raymond Horton, Chiraq Patel, Edmund Sprogis, Brian Sundlof
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Publication number: 20030115750Abstract: A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.Type: ApplicationFiled: February 10, 2003Publication date: June 26, 2003Applicant: International Business Machines CorporationInventors: Edward W. Conrad, Chung H. Lam, Dale W. Martin, Edmund Sprogis
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Patent number: 6566759Abstract: A structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.Type: GrantFiled: August 23, 1999Date of Patent: May 20, 2003Assignee: International Business Machines CorporationInventors: Edward W. Conrad, Chung H. Lam, Dale W. Martin, Edmund Sprogis
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Patent number: 6452265Abstract: A multi-chip module is constructed by aligning prewired chips on a support wafer and depositing a nonconductive thermally conductive and electrically nonconductive material having a coefficient of thermal expansion that approximate that of the chips (e.g. silicon, silicon carbide, silicon germanium, germanium or SiCGe) to surround chips. After removal of the support wafer, processing of multi-chip module is finished with wiring on a shared surface of multi-chip module and chip surface.Type: GrantFiled: January 28, 2000Date of Patent: September 17, 2002Assignee: International Business Machines CorporationInventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Rosemary A. Previti-Kelly, Edmund Sprogis