Abstract: A system and method are provided for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture. The method comprises providing multiple representation states, each representation state providing a representation in the host architecture for at least one item of state from the guest architecture. A current representation state is then determined from amongst the multiple representation states, and the guest instruction is translated into at least one host instruction in dependence on the current representation state. Through the use of multiple representation states, it has been found that the efficiency of the code translation can be significantly increased, thereby giving rise to performance and energy consumption benefits.

Abstract: There is provided an apparatus that includes processing circuitry for performing processing operations specified by program instructions and a target register that stores a target program address. A value register stores a data value. There is also provided an architectural register and an instruction decoder that decodes the program instructions to generate control signals to control the processing circuitry to perform the processing operations. The instruction decoder includes branch instruction decoding circuitry that decodes a register restoring branch instruction to cause the processing circuitry to determine whether the target program address and the data value are valid. If the target program address and the data value are both valid then the processing circuitry is caused to branch to the target program address and update the architectural register to store the data value. Otherwise an error action is taken.

Abstract: There is provided an apparatus that includes processing circuitry for performing processing operations specified by program instructions and a target register that stores a target program address. A value register stores a data value. There is also provided an architectural register and an instruction decoder that decodes the program instructions to generate control signals to control the processing circuitry to perform the processing operations. The instruction decoder includes branch instruction decoding circuitry that decodes a register restoring branch instruction to cause the processing circuitry to determine whether the target program address and the data value are valid. If the target program address and the data value are both valid then the processing circuitry is caused to branch to the target program address and update the architectural register to store the data value. Otherwise an error action is taken.

Abstract: A system and method are provided for translating a guest instruction of a guest architecture into at least one host instruction of a host architecture. The method comprises providing multiple representation states, each representation state providing a representation in the host architecture for at least one item of state from the guest architecture. A current representation state is then determined from amongst the multiple representation states, and the guest instruction is translated into at least one host instruction in dependence on the current representation state. Through the use of multiple representation states, it has been found that the efficiency of the code translation can be significantly increased, thereby giving rise to performance and energy consumption benefits.