Abstract: An apparatus for cooling an integrated circuit chip that comprises an air movement device, a plurality of mounting clips, and a plurality of fasteners. The mounting clips are for clipping the air movement device onto the integrated circuit chip. The fasteners fix the mounting clips to the air movement device. In addition, these fasteners have heads that provide spacing between the air movement device and the integrated circuit chip when the air movement device is clipped onto the integrated circuit chip by the mounting clips. This allows air to be moved over the integrated circuit chip by the air movement device in order to cool the integrated circuit chip.

Abstract: A compressed memory address parity (CMAP) checking apparatus for checking the parity of data read from a data memory comprising a low capacity auxiliary memory with 2.sup.N address spaces and an adaptive auxiliary memory addressing scheme to reduce the amount of memory required to perform parity checking. When data is stored in the data memory at an address MA having M bits, (M-N) bits of the data memory address together with one or more parity bits generated from the data stored in the data memory is stored in the auxiliary memory at an address given by the remaining N bits of the data memory address. When data is read from an address MA in the data memory, the (M-N) bits at the address N in the auxiliary memory is compared with the corresponding (M-N) bits in the data memory address. If there is a match, the one or more parity bits stored in the auxiliary memory are read.

Abstract: A memory module, parity bit emulator, and method which emulate storing and retrieving a parity bit from memory. The memory module includes a memory for storing a data word which is retrieved from the memory during the read cycle. The memory module also includes a parity bit emulator which includes a parity bit generator. The parity bit generator is responsive to the retrieved data word and generates in response a corresponding parity bit during the read cycle. The memory module also includes an input/output port for outputting the retrieved data word and the generated parity bit during the read cycle.