Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: Embodiments of the present invention can selectively enable 16 lane (×16) or 8 lane (×8) device testing using multiplexor circuitry disposed between a CXL1.1 CPU and the DUTs during testing. In this way, parallelism and testing efficiency are significantly improved compared to existing approaches that can only test devices using 8 lanes of the CXL 1.1 CPU.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs), and a hardware interface board coupled to the test computer system and controlled by the test computer system. The hardware interface board is operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs, the hardware interface board including: a processor operable to access test pattern data for application to a DUT.

Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

Abstract: An automated test equipment (ATE) system comprises a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The FPGA is communicatively coupled to the tester processor, wherein the FPGA is configured to internally generate commands and data transparently from the tester processor for testing a DUT. Further, the system comprises a demultiplexer positioned between the DUT and the FPGA, wherein, responsive to a determination that the DUT is operating in a high speed mode, the demultiplexer is configured to channel data traffic from the DUT to a Serializer/Deserializer (SerDes) receiver on the FPGA, and further wherein, responsive to a determination that the DUT is operating in a low speed mode, the demultiplexer is configured to channel data traffic from the DUT to input buffers on the FPGA with switchable on/off input terminations.

Abstract: An automated test equipment (ATE) system comprises a system controller, wherein the system controller is communicatively coupled to a tester processor and an FPGA. The FPGA is communicatively coupled to the tester processor, wherein the FPGA is configured to internally generate commands and data transparently from the tester processor for testing a DUT. Further, the system comprises a demultiplexer positioned between the DUT and the FPGA, wherein, responsive to a determination that the DUT is operating in a high speed mode, the demultiplexer is configured to channel data traffic from the DUT to a Serializer/Deserializer (SerDes) receiver on the FPGA, and further wherein, responsive to a determination that the DUT is operating in a low speed mode, the demultiplexer is configured to channel data traffic from the DUT to input buffers on the FPGA with switchable on/off input terminations.

Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Abstract: In one embodiment, an automated test equipment (ATE) system includes a tester having a tester electronics module, an application specific electronics module, and a tester-to-device under test (DUT) interface mount. The tester electronics module has a first electronics interface configured to electrically connect to a tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module has a second electronics interface and a third electronics interface. The second and third electronics interfaces are configured to electrically connect to the tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module is configured to communicate with the tester electronics module via the second electronics interface, and with at least one DUT via the third electronics interface.

Abstract: Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.

Abstract: ATE performs testing of memory devices with distributed processing operations. A redundancy analysis (RA) system has a first test site processor (TSP), operable for controlling a testing routine over multiple DUTs and analyzing redundancy data returned from a first of the DUTs. The RA has at least a second TSP, operable for analyzing redundancy data returned from a second of the DUTs. The RA may have one or more additional TSPs, each operable for analyzing redundancy data returned from an additional DUT. Controlling the testing routine includes directing the RA in each of the first and second (and any of the additional) TSPs.

Abstract: An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Abstract: In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed.

Abstract: In one embodiment, an automated test equipment (ATE) system includes a tester having a tester electronics module, an application specific electronics module, and a tester-to-device under test (DUT) interface mount. The tester electronics module has a first electronics interface configured to electrically connect to a tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module has a second electronics interface and a third electronics interface. The second and third electronics interfaces are configured to electrically connect to the tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module is configured to communicate with the tester electronics module via the second electronics interface, and with at least one DUT via the third electronics interface.

Abstract: In accordance with one embodiment of the invention, a system is provided that comprises a first terminal for receiving an input testing signal during operation; a plurality of input/output terminals coupled with the first terminal; wherein the input/output terminals are configured to parallel output respective output testing signals during parallel output operation; wherein the input/output terminals are configured to parallel input testing response signals during parallel input operation from devices under test; and wherein each of the input/output terminals is electrically isolated during operation from the remaining plurality of input/output terminals.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.

Abstract: In one embodiment, apparatus for transmitting and receiving data includes a transmission line network having at least three input/output terminals; at least three transmit/receive units, respectively coupled to the at least three input/output terminals; and a control system. The control system is configured to, depending on a desired direction of data flow over the transmission line network, i) dynamically place each of the transmit/receive units in a transmit mode or a receive mode, and ii) dynamically enable and disable an active termination of each transmit/receive unit. Methods for using this and other related apparatus to transmit and receive data over a transmission line network are also disclosed.

Abstract: An active routing circuit. In representative embodiments, the active routing circuit includes a channel switch which includes a transceiver and a switch. The transceiver has first data line, second data line, drive/receive control line, and receiver select control line. The switch has first contact connected to first data line, second contact connected to second data line, and switch control line. In a driver mode, the transceiver can receive data from first data line and output that data to second data line, and in receiver mode, can receive data from second data line and output that data to first data line. The transceiver can switch between driver mode and receiver mode in response to a signal. Data received from the second data line can be blocked in response to another signal. The switch can shift between connecting and disconnecting first contact to/from second contact in response to yet another signal.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.

Abstract: In one embodiment, apparatus for testing at least one device under test (DUT) includes a tester input/output (I/O) node, a DUT I/O node, a remote pin electronics block, a bypass circuit, and a control system. The remote pin electronics block provides a test function and is coupled between the tester I/O node and the DUT I/O node. The bypass circuit is coupled between the tester I/O node and the DUT I/O node and provides a signal bypass path between the tester I/O node and the DUT I/O node. The signal bypass path bypasses the test function provided by the remote pin electronics block. The control system is configured to enable and disable the bypass circuit. Methods for using this and other related apparatus to test one or more DUTs are also disclosed.