Patents by Inventor EDNA FANG

EDNA FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Circuit screening system and circuit screening method
    Patent number: 11500016
    Abstract: A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chi-Che Wu, Tsung-Yang Hung, Jia-Ming Guo, Edna Fang, Ming-Yih Wang
  • CIRCUIT SCREENING SYSTEM AND CIRCUIT SCREENING METHOD
    Publication number: 20220178998
    Abstract: A circuit screening system includes a target circuit under test, a power circuit, and a clock generating circuit. The target circuit under test receives a first testing signal in a first period, and a second testing signal in a second period, and the first testing signal is different from the second testing signal. The power circuit provides a supply voltage to the target circuit under test, wherein a voltage level of the supply voltage maintains at a first voltage level in the first period, is pulled up to a second voltage level and back to the first level after the first period, and maintains at the first voltage level in a second period after the first period. The clock generating circuit provides a clock signal to the target circuit under test, wherein the clock signal has different profiles in the first period and the second period.
    Type: Application
    Filed: December 7, 2020
    Publication date: June 9, 2022
    Inventors: CHI-CHE WU, TSUNG-YANG HUNG, JIA-MING GUO, EDNA FANG, MING-YIH WANG