Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a current protection controller to: receive instruction width information and instruction type information associated with one or more instructions stored in an instruction queue prior to execution of the one or more instructions by an execution circuit; determine a power license level for the core based on the corresponding instruction width information and the instruction type information; generate a request for a license for the core corresponding to the power license level; and communicate the request to a power controller when the one or more instructions are non-speculative, and defer communication of the request when at least one of the one or more instructions is speculative. Other embodiments are described and claimed.