Patents by Inventor Edouard Giacomin
Edouard Giacomin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11677401Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cellType: GrantFiled: May 10, 2022Date of Patent: June 13, 2023Assignee: IMEC VZWInventors: Francky Catthoor, Edouard Giacomin, Juergen Boemmels, Julien Ryckaert
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Patent number: 11450385Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.Type: GrantFiled: September 20, 2019Date of Patent: September 20, 2022Assignee: UNIVERSITY OF UTAH RESEARCH FOUNDATIONInventors: Pierre-Emmanuel Gaillardon, Edouard Giacomin, Joao Vieira
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Publication number: 20220271755Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cellType: ApplicationFiled: May 10, 2022Publication date: August 25, 2022Inventors: Francky CATTHOOR, Edouard GIACOMIN, Juergen BOEMMELS, Julien RYCKAERT
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Patent number: 11381242Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cellType: GrantFiled: October 5, 2020Date of Patent: July 5, 2022Assignee: IMEC VZWInventors: Francky Catthoor, Edouard Giacomin, Juergen Boemmels, Julien Ryckaert
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Publication number: 20220109447Abstract: According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cellType: ApplicationFiled: October 5, 2020Publication date: April 7, 2022Inventors: Francky CATTHOOR, Edouard GIACOMIN, Juergen BOEMMELS, Julien RYCKAERT
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Publication number: 20200098428Abstract: One embodiment provides a resistive random-access memory (RRAM) based convolutional block including a complementary pair of RRAMs having a first RRAM and a second RRAM, a programming circuit coupled to the complementary pair of RRAMs, and a XNOR sense amplifier circuit coupled to the complementary pair of RRAMs. The programming circuit is configured to receive a kernel bit from a kernel matrix, program the first RRAM to at least one selected from a group consisting of a low resistive state (LRS) and a high resistive state (HRS) based on the kernel bit, and program the second RRAM to other of the LRS and the HRS. The XNOR sense amplifier circuit is configured to receive an input bit from an input matrix, perform a XNOR operation between the input bit and the kernel bit read from the complementary pair of RRAMs, and output a XNOR output based on the XNOR operation.Type: ApplicationFiled: September 20, 2019Publication date: March 26, 2020Inventors: Pierre-Emmanuel Gaillardon, Edouard Giacomin, Joao Vieira
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Patent number: 10348306Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.Type: GrantFiled: March 9, 2018Date of Patent: July 9, 2019Assignees: University of Utah Research Foundation, Ecole Polytechnique Federale de Lausanne (EPFL)Inventors: Pierre-Emanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli, Edouard Giacomin
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Publication number: 20180262197Abstract: Resistive random access memory (RRAM) based multiplexers and field programmable gate arrays (FPGAs) are provided. The RRAM-based multiplexers and FPGAs include a 4T1R programming structure to program the RRAMs. The programming structure includes two programming transistors connected between the power supply and the top electrode of the RRAM and two programming transistors connected between the power supply and the bottom electrode of the RRAM. The programming transistors are used to set and rest the RRAMs. In the RRAM-based multiplexer programming transistors connected to the bottom electrodes are shared between a plurality of RRAMs. The shared programming transistors and an output inverter of the RRAM are provided in a deep N-well of the RRAM-based multiplexer. The programming transistors connected to the top electrodes of the RRAMs and a plurality of input inverters are provided in a regular well of the RRAM-based multiplexer.Type: ApplicationFiled: March 9, 2018Publication date: September 13, 2018Inventors: Pierre-Emanuel Gaillardon, Xifan Tang, Gain Kim, Giovanni De Micheli, Edouard Giacomin