Abstract: An integratable transformer circuit for converting an asymmetrical input signal into a pair of symmetrical output signal currents and requiring only one IC connection pin. The circuit exhibits a low input impedance combined with good noise, gain and intermodulation performance up to high frequencies. The asymmetrical input terminal of the circuit is coupled to a node commonly coupled to the emitter of a common base transistor and to the base of a common emitter transistor. The common base transistor acts as a non-inverting current follower, the common emitter transistor as an inverting transimpedance amplifier. An input signal current is transferred to a first symmetrical output terminal via the node and the common base transistor, thereby producing a signal voltage at the node. This signal voltage modulates the collector current of the common emitter transistor, which is in phase opposition to the input signal current and is transferred to the second output terminal.

Abstract: A receiver including two sigma delta modulators used to convert a pair of analog quadrature signals into digital quadrature signals. In such sigma delta modulators the quantization noise is shifted into a frequency region in which no signal is present. A cross coupling between the filters is provided to improve the noise reduction without increasing the order of the filters. By providing the cross coupling, it is possible to obtain complex poles and zeros in the noise transfer function which do not have to appear in complex conjugate pairs which results in an increase of the noise suppression in a specified frequency range.

Abstract: In a television receiver a SAW filter (FSAW) is preceded by a coupling network (CNW). The coupling network (CNW) includes an inductor (LP) between two input terminals of the SAW filter (IS1, IS2). It further includes a series resonance circuit (SRC) coupled to at least one of the input terminals (IS1). In order to reduce signal distortion a resistor (RP) is coupled between the two input terminals (IS1, IS2). Alternatively, a resistor (RS) is coupled in parallel to the series resonance circuit (SRC).

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.1, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E.sub.1, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from the relative positions (tf/T) and the phase values (F).

Abstract: A digital phase-locked-loop circuit is provided for deriving from a sequence of samples (J.sub.1, . . . J.sub.20) of a band-limited data signal (Vt), the phase of the data signal at the sampling instants. The circuit includes a discrete-time oscillator 10 for generating a sequence of phase values (F.sub.2, . . . F.sub.20) which characterize a periodic signal (Vk1) having an amplitude which varies as a linear function of time between two constant limit values (E, -E). The frequency of the periodic signal (Vk1) characterized by the phase values is proportional to a control value (I). An interpolation circuit (2) derives from the samples (J.sub.1, . . . J.sub.20) the relative positions (tf/T) occupied by the detection-level crossings of the data signal (Vt) relative to the sampling instants. A phase detector (3) derives the difference (.DELTA.F) between the actual phase of the data signal (Vt) and the phase as indicated by the phase values (F) from said relative positions (tf/T) and the phase values (F).

Abstract: In a sample rate converter having a non-rational conversion factor the input samples coincide with low-rate clock pulses and the output samples coincide with high-rate clock pulses, or inversely. It comprises a filter coefficient generator which, based on the distance (deviation) between a low-rate clock pulse and the immediately preceding or immediately subsequent high-rate clock pulse, continuously supplies a series of filter coefficients. To determine the deviation a phase-locked loop is provided, with a phase detector receiving the low-rate clock pulses as well as synthetic low-rate clock pulses and supplying a discrete-time phase difference signal which is applied to a processor circuit. This circuit supplies the desired deviation and a reference number which is applied to a counter circuit. This circuit also receives the high-rate clock pulses and each time after receiving the number of clock pulses corresponding to the reference number it supplies a synthetic low-rate clock pulse.

Abstract: A time-discrete amplitude-continuous or a time-discrete amplitude-discrete signal is converted in to a 1-bit encoded signal by means of a quantizer, the quantization-error signal being fed back via a loop filter. The transfer function of the loop filter is given by H(Z)=1-(Z-b).sup.n /(Z-a).sup.n, where n.gtoreq.3, b.perspectiveto.1 and 0<a<b. In order to preclude, the input signal of the loop filter is limited by a limiter.

Abstract: An integrated data processor which includes a multiplier element provided with non-symmetrical operand inputs and an arithmetic and logic unit which is connected to the output of the multiplier element by way of a connection over the full product width. The ALU also comprises an accumulator device. Multiple-precision operations can thus be performed on the quantities received on each of the two inputs of the multiplier element. The data processor is notably suitable for performing each time identical operations on sequentially arriving signal quantities.

Abstract: Interpolating time-discrete filter arrangement for increasing the sampling frequency of a time-discrete signal from f.sub.i to f.sub.u, f.sub.u not being a rational multiple of f.sub.i. For the generation of the required filter coefficients this filter arrangement comprises clock pulse generators which produce input clock pulses ki(q) at a rate f.sub.i and output clock pulses ku(n) at a rate f.sub.u. It also comprises a coefficients generator in which a deviation component d(q) is calculated which indicates the relationship between the time interval T.sub.d(q) located between an input clock pulse k.sub.i (q) and the immediately preceding or the immediately subsequent output clock pulse ku(n) and the time interval T.sub.u =1/f.sub.u between two consecutive output clock pulses ku(n). In response to this deviation component the filter coefficients generator produces W filter coefficients, the w.sup.th filter coefficient (w=0, 1, 2, 3, . . .

Abstract: By the use of high-resistivity polycrystalline silicon (poly) in MIS elements, a depletion layer can be formed in the poly material which brings about an electric decoupling between the poly (gate) and the underlying semiconductor body. This effect can be utilized advantageously in various circuit elements, such as in CCD's, in order to obtain a favorable potential distribution in the substrate; in MOS transistors in order to reduce the parasitic capacities; and in high-voltage devices in order to increase the breakdown voltage at the edge of the field plate (resurf).

Abstract: A decimation filter arrangement for reducing the sampling frequency of a time-discrete input signal from f.sub.i to f.sub.u, f.sup.u not being a rational portion of f.sub.i. For the generation of the required filter coefficients this arrangement comprises clock pulse generators producing first clock pulses ki(.) at a rate f.sub.i and second clock pulses au(.) at a rate f.sub.u. The arrangement also comprises a coefficients generator in which a deviation component d.sub.n is calculated which indicates the ratio between the time interval located between a clock pulse au(.) and the immediately preceding clock pulse ki(.), and the time interval 1/f.sub.i between two consecutive clock pulses ki(.). In response to this deviation component this coefficients generator produces N vilter coefficients, the m.sup.th filter coefficient, m=0, 1, 2, . . . N-1, being equal to a.sub.n (m)=h[(d.sub.n +m)V.sub.o ].

Abstract: A digital dynamic range converter of the forward control type for varying the dynamic range of a digital audio signal constituted by a sequence of audio signal samples. Each audio signal sample x(n) is multiplied by a control signal sample s(n) which is delivered by a digital control signal generator. This control signal generator has applied to it unipolar signal samples x(n) which are derived via a transmission channel from the audio signal samples x(n). In order to cause this dynamic range converter to respond rapidly to abrupt variations in the audio signal and to render it moreover universally usable, the control signal generator is provided with a digital peak-value detector which converts the sequence of unipolar signal samples x(n) into a sequence of peak-value samples x(n). The latter are applied to a digital non-linear amplitude transformation circuit which has an adjustable amplitude transmission characteristic curve determined by adjustment quantities R and a.

Abstract: A mixer comprises a MOS transistor having an ideal quadratic characteristic. The transistor is of the D-MOST type and comprises a resistive gate across which a voltage drop is applied transversely to the longitudinal direction of the channel. The adjustment point of the transistor is chosen to be so that the range of the gate voltages between the threshold voltage and the voltage at which the slope reaches the saturation value is always situated during operation within the voltage drop across the gate electrode. The signals to be mixed are introduced capacitively via a second gate electrode situated above the resistive gate electrode and capacitively coupled therewith.