Patents by Inventor EDUARD J. PABST

EDUARD J. PABST has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9589909
    Abstract: Radio frequency/electromagnetic interference (RF/EMI) shielding within redistribution layers of a fan-out wafer level package is provided. By using RDL metal layers to provide the shielding, additional process steps are avoided (e.g., incorporating a shielding lid or applying conformal paint on the package back side). Embodiments use metal filled trench vias in the RDL dielectric layers to provide metal “walls” around the RF sensitive signal lines through the dielectric layer regions of the RDL. These walls are coupled to ground, which isolates the signal lines from interference or noise generated outside the walls.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: March 7, 2017
    Assignee: NXP USA, INC.
    Inventors: Weng F. Yap, Eduard J. Pabst
  • Patent number: 9502363
    Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: November 22, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael B. Vincent, Trung Q. Duong, Zhiwei Gong, Scott M. Hayes, Alan J. Magnus, Douglas G. Mitchell, Eduard J. Pabst, Jason R. Wright, Weng F. Yap
  • Patent number: 9362234
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: June 7, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Eduard J. Pabst, Sergio P. Pacheco, Weng F. Yap
  • Patent number: 9343414
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 17, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weng F. Yap, Eduard J. Pabst
  • Publication number: 20150348920
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.
    Type: Application
    Filed: August 13, 2015
    Publication date: December 3, 2015
    Applicant: FREESCALE SEMICONDUCTOR INC.
    Inventors: WENG F. YAP, EDUARD J. PABST
  • Publication number: 20150270233
    Abstract: Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Inventors: MICHAEL B. VINCENT, TRUNG Q. DUONG, ZHIWEI GONG, SCOTT M. HAYES, ALAN J. MAGNUS, DOUGLAS G. MITCHELL, EDUARD J. PABST, JASON R. WRIGHT, WENG F. YAP
  • Patent number: 9129981
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: September 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Weng F. Yap, Eduard J. Pabst
  • Publication number: 20150194388
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a conductive interconnect structure within the molding compound, a conductive frame structure laterally surrounding the one or more electrical components and the interconnect structure, and a shielding structure overlying the one or more electrical components. The shielding structure is electrically connected to the frame structure and at least a portion of the molding compound resides between the shielding structure and the one or more electrical components.
    Type: Application
    Filed: January 7, 2014
    Publication date: July 9, 2015
    Inventors: EDUARD J. PABST, SERGIO P. PACHECO, WENG F. YAP
  • Publication number: 20150145108
    Abstract: Microelectronic packages and methods for fabricating microelectronic packages are provided. In one embodiment, the method includes producing a plurality of vertically-elongated contacts in ohmic contact with interconnect lines contained within one or more redistribution layers built over the frontside of a semiconductor die. A molded radiofrequency (RF) separation or stand-off layer is formed over the redistribution layers through which the plurality of vertically-elongated contacts extend. An antenna structure is fabricated or otherwise provided over the molded RF stand-off layer and electrically coupled to the semiconductor die through at least one of the plurality of vertically-elongated contacts.
    Type: Application
    Filed: November 26, 2013
    Publication date: May 28, 2015
    Inventors: WENG F. YAP, EDUARD J. PABST
  • Publication number: 20150108621
    Abstract: Shielded device packages and related fabrication methods are provided. An exemplary device package includes one or more electrical components, a molding compound overlying the one or more electrical components, a frame structure circumscribing the one or more electrical components, and a shielding structure overlying the frame structure and the one or more electrical components. The shielding structure contacts a first surface of the frame structure, at least a portion of the molding compound resides between the shielding structure and the one or more electrical components, and the first surface of the frame structure is aligned with a second surface of the portion of the molding compound.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 23, 2015
    Inventors: EDUARD J. PABST, ZHIWEI GONG