Patents by Inventor Eduard VARDANYAN

Eduard VARDANYAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10810146
    Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 20, 2020
    Assignee: ARM LIMITED
    Inventors: Arthur Brian Laughton, Chiranjeev Acharya, Eduard Vardanyan
  • Patent number: 10740032
    Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 11, 2020
    Assignee: Arm Limited
    Inventors: Chiranjeev Acharya, Sean James Salisbury, Eduard Vardanyan, Arthur Brian Laughton
  • Patent number: 10628335
    Abstract: Processing circuitry 2 includes data storage circuitry 18 for storing one or more ordered sets of data entries. Access control circuitry 20 controls access during a given access cycle to a given ordered set of data entries in dependence upon, for that given set of data entries, a head-entry flag, a next-following-entry flag and preceding-cycle data. The head-entry flag indicates the oldest data entry for the given ordered set, the next-following-entry flag indicates the next oldest entry and the preceding-cycle flag indicates whether the given ordered set was accessed during a preceding access cycle. If the given ordered set was accessed during the preceding access cycle, then the next-following entry corresponding to the next-following flag is accessed during the current access cycle instead of that indicated by the head flag.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: April 21, 2020
    Assignee: ARM Limited
    Inventors: Jaume Cabecerans Betran, Eduard Vardanyan
  • Patent number: 10437750
    Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 8, 2019
    Assignee: ARM Limited
    Inventors: Arthur Brian Laughton, Sean James Salisbury, Chiranjeev Acharya, Eduard Vardanyan
  • Publication number: 20190196990
    Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Arthur Brian LAUGHTON, Sean James SALISBURY, Chiranjeev ACHARYA, Eduard VARDANYAN
  • Publication number: 20190179783
    Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.
    Type: Application
    Filed: November 26, 2018
    Publication date: June 13, 2019
    Inventors: Arthur Brian LAUGHTON, Chiranjeev ACHARYA, Eduard VARDANYAN
  • Publication number: 20190163400
    Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.
    Type: Application
    Filed: October 1, 2018
    Publication date: May 30, 2019
    Inventors: Chiranjeev ACHARYA, Sean James SALISBURY, Eduard VARDANYAN, Arthur Brian LAUGHTON
  • Publication number: 20190073321
    Abstract: Processing circuitry 2 includes data storage circuitry 18 for storing one or more ordered sets of data entries. Access control circuitry 20 controls access during a given access cycle to a given ordered set of data entries in dependence upon, for that given set of data entries, a head-entry flag, a next-following-entry flag and preceding-cycle data. The head-entry flag indicates the oldest data entry for the given ordered set, the next-following-entry flag indicates the next oldest entry and the preceding-cycle flag indicates whether the given ordered set was accessed during a preceding access cycle. If the given ordered set was accessed during the preceding access cycle, then the next-following entry corresponding to the next-following flag is accessed during the current access cycle instead of that indicated by the head flag.
    Type: Application
    Filed: July 18, 2018
    Publication date: March 7, 2019
    Inventors: Jaume Cabecerans BETRAN, Eduard VARDANYAN