Abstract: In a communication data stream transmitted within IP datagrams via a communication network, the timing of the transmission of the IP datagrams is oriented toward a timestamp which is transmitted to a transmitter of the IP datagrams. In this context, the transmitter reserves time intervals whose timing is geared to the received timestamp for the purpose of transmitting the IP datagrams. The IP datagrams are respectively assigned to one of the time intervals and are transmitted within the respectively associated time interval by the transmitter in line with the Internet protocol.

Abstract: Time information which is to be transmitted via a data packet network is called up from a time information source and is transmitted to a data packet transmission module. The data packet transmission module controls the transmission time of a data packet in which the time information is transmitted via the data packet network. The transmission time and the calling of the time information are aligned with respect to one another in time by a transmission signal which is generated by the time information source or by the data packet transmission module and indicates the transmission time.

Abstract: A node device for a serial databus connecting a number of devices, having in each case three input and output units, in which case a second output unit of the node device can, in each case, be connected to a first input unit of a second node device of the databus. A third output unit of the node device can be connected to an input unit of a device, and a third input unit of the node device can be connected to an output unit of the device. The node device contains a multiplexer for connecting the first or third input unit to the second output unit of the node device and, furthermore, a detector, which is coupled to the first input unit, to the third input unit and to the multiplexer, for detection of an incoming data stream at the first and/or third input unit for appropriate control of the connection of the multiplexer.

Abstract: To synchronize a controllable oscillator with a first reference clock signal, a first phase locked loop having a first phase comparison device is provided. In addition, the synchronous-frequency clock signal from the oscillator is supplied to a second phase comparison device for phase comparison with a second reference clock signal via an inventive phase control element for inserting and removing clock phases. On the basis of the output signal from the second phase comparison device, phase correction information is formed and on the basis of this phase correction information the insertion and removal of clock phases is controlled in the phase control element. If the first reference clock signal disappears, the oscillator is stabilized using the second reference clock signal by taking into account the phase correction information formed previously.

Abstract: To synchronize a communication system via a packet-oriented data network, a frequency offset of a time-measuring device is determined by a measuring device using only data packets with approximately the same forward and return times.

Abstract: Time information which is to be transmitted via a data packet network is called up from a time information source and is transmitted to a data packet transmission module. The data packet transmission module controls the transmission time of a data packet in which the time information is transmitted via the data packet network. The transmission time and the calling of the time information are aligned with respect to one another in time by a transmission signal which is generated by the time information source or by the data packet transmission module and indicates the transmission time.

Abstract: In a communication data stream transmitted within IP datagrams via a communication network, the timing of the transmission of the IP datagrams is oriented toward a timestamp which is transmitted to a transmitter of the IP datagrams. In this context, the transmitter reserves time intervals whose timing is geared to the received timestamp for the purpose of transmitting the IP datagrams. The IP datagrams are respectively assigned to one of the time intervals and are transmitted within the respectively associated time interval by the transmitter in line with the Internet protocol.

Abstract: A node device for a serial databus connecting a number of devices, having in each case three input and output units, in which case a second output unit of the node device can, in each case, be connected to a first input unit of a second node device of the databus. A third output unit of the node device can be connected to an input unit of a device, and a third input unit of the node device can be connected to an output unit of the device. The node device contains a multiplexer for connecting the first or third input unit to the second output unit of the node device and, furthermore, a detector, which is coupled to the first input unit, to the third input unit and to the multiplexer, for detection of an incoming data stream at the first and/or third input unit for appropriate control of the connection of the multiplexer.

Abstract: A method and arrangement for determining the phase difference between two timing signals provides that the first timing signal is ed to a delay line multiple times, whereby the number of passes through the delay line is obtained. The phase difference is determined in that a first transit time information is determined that corresponds to that number of delay elements of the delay line that are passed through by the first timing signal during a differential time-span between the two timing signals. Second transit time information is further obtained corresponding to that number of delay elements passed through by the first timing signal during a timing pulse period of time second timing signal. The determination of the first and second transit time information occurs dependent on the number of total passes of the first timing signal through the delay line, respectively, which is obtained at the respective determination time.

Abstract: The method determines the phase difference in phase locked loops using clock signals (ts) generated in clock generators of communication equipment are synchronized to incoming reference clock signals (rts). The phase difference is determined by a rough phase difference and by a fine phase difference. The fine phase difference is represented by the plurality of delay elements (VE) of a delay line (VZL) that an incoming reference clock signal (rts) traverses up to the following clock signal (ts). A precise determination of the absolute delay time of a delay element (VE) is possible using the method, whereby components' tolerances cause considerable delay time differences of a delay element (VE) or, respectively, of the delay line (VZL). A considerable enhancement of the precision in determining the phase difference of cloak signals (ts) and reference clock signals (rts) and, thus, of the phase locked loops is achieved by the more precise determination of the absolute delay time of a delay element (VE).

Abstract: In an oscillator circuit (VCOS) that contains an oscillator crystal having characteristic information (ki) individually associated to the oscillator crystal, the crystal signals or digital clock signals (ts) are conducted to an output (A). A memory that stores the individual characteristic information (ki) of the oscillator crystal is fashioned in the oscillator circuit (VCOS) such that the individual characteristic information (ki) of the oscillator crystals are moved to at least one output (A, AM) of the oscillator circuit (VCOS) as analog, digital, coded digital or modulated signals (msp).

Abstract: In an oscillator circuit (VCOS) having at least one heating element (HE) that keeps the temperature constant, the clock signals (ts) that are formed are conducted via an output connection (AV) to an output (TA) of the oscillator circuit (VCOS). An impedance evaluation unit (WAE) is inserted into this output connection (AV) and detects changes in an impedance or of a resistor (R4, R5) connected to the output (TA) and the heating element (HE) is activated or deactivated in response to changes in the impedance.

Abstract: At least one connection for the communication exchange and one connection for the communication of frame clock signals is provided between centralized equipment, for example a switching matrix network, and decentralized equipment, for example line trunk groups. The frame clock signals indicate the beginning of a transmission frame utilized for the channel-oriented communication exchange. The operating condition information, for example equipment is "active" or "inactive" are communicated by pulse-duration or pulse-pause modulated or by n-coded pulse duration or pulse-pause-modulated frame clock signals.

Abstract: Method for synchronizing the phase of clock signals of two clock generators in communications networks. Using the present method, the phase relations of clock signals that are derived from oscillator clock signals in two clock generators are synchronized such that the phase relations of the clock signals coincide regardless of the distance between the two clock generators. To this end, one clock generator is defined as a reference clock generator and reference clock signals formed therein are communicated to the other further clock generator. In the latter, the generated further clock signals are synchronized with the incoming reference clock signals and the clock signals synchronized in this fashion are forwarded to the reference clock generator. In the latter, the phase deviation of the internally formed clock signals and of the incoming clock signals is measured and correction information is formed and forwarded to the other further clock generator.

Abstract: A heating or, respectively, cooling device is realized by a Peltier element and is assigned to a crystal oscillator and driven by a processor with the assistance of a temperature sensor such that the crystal exhibits one of two selected temperatures lying closest to the ambient temperature. A compensation value is stored in the memory of the processor for each of the crystal temperatures selected from an operating temperature range. This compensation value effects the compensation of the frequency deviations of the crystal oscillator that are caused by temperature fluctuations.

Abstract: A phase-locked loop is formed by a series circuit of a counter, a register, an arithmetic unit, a low-pass filter, a PI-filter, and a voltage-controlled oscillator. The digital, internal clock signals generated by the oscillator are counted in a counter and are transferred into the register and stored as a current counter reading at points in time determined by time interval clock signals. For example, the time interval clock signals are acquired from reference clock signals by means of a divider and exhibit a lower frequency than the internal clock signals. A drive signal in digital form is determined in the arithmetic unit on the basis of the current counter reading, on the counter reading of the preceding evaluation interval, and on a rated value. This drive signal proceeds via a digital low-pass filter, PI-filter, and D/A converter to the control input of the oscillator, and controls the latter such that the internal clock signals coincide in phase with the reference clock signals.

Abstract: In addition to a filter phase comparator, an integrator, a first filter and a voltage-controlled oscillator of relatively low stability and having a wide pull-in range, a circuit arrangement for generating a clock signal comprises a frequency generator of high stability having a narrow pull-in range, a second phase comparator and second and third filters. The first phase comparator is supplied with the reference frequency and the clock signal emitted by the voltage-controlled oscillator. The second phase comparator is supplied with the clock signal and a normal frequency generated by a normal frequency generator. In the event of the failure of the reference frequency or the overshooting of predetermined phase difference values, a regulating circuit formed by the second phase comparator, the second filter, the third filter and the voltage-controlled oscillator is closed.

Abstract: After the initiation of the offering of additional telephone paths or audible signals, the existing telephone connection is reswitched onto two subscriber inputs of a conference or offering device provided with the conference switching matrix array and arranged in a peripheral unit being reswitched by way of control devices and switching matrix arrays arranged in digital telephone switching systems. The two subscribers are connected via a preset conference switching matrix array. The additional telephone paths or audible signals are conducted to a further subscriber input of the conference or offering device with the assistance of the control devices and with the assistance of the switching matrix arrays and are designationally switched onto the existing connection in the conference or offering device via the conference switching matrix array.

Abstract: A method for connecting subscribers to form a conference call in a time division multiplex (TDM) telecommunication switching system having a TDM ring-like circuit running from subscriber to subscriber is described. A subscriber speech word is added to a pulse code modulated (PCM) word transferred to the subscriber station, and the summation PCM word is both retransferred and stored in the subscriber station for a time-slot frame. The stored preceding PCM word is subtracted from the PCM word transferred to the subscriber station, and the differential PCM word forms an aural signal.

Abstract: An analog signal PCM signal/PCM signal-analog signal converter having a sawtooth generator, the sawtooth voltage of which is compared in a first comparator with the analog signal to be converted, the sawtooth signal being represented in instantaneous amplitude by code chains provided by a register which also provides timing pulses coincident with the pulse rate of the PCM signals. The analog comparator controls the forwarding of the code chain corresponding to the analog signal to be converted and delivered through a compandor which allows for non-linear signals.Incoming PCM signals are compared with the code chains as fed through the compandor in a digital comparator which utilizes a positive result to gate the sawtooth voltage output and generate an analog signal.