Patents by Inventor Eduardo Quinones

Eduardo Quinones has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9396119
    Abstract: The present disclosure relates to a device for controlling the access to a cache structure comprising multiple cache sets during the execution of at least one computer program, the device comprising a module for generating seed values during the execution of the at least one computer program; a parametric hash function module for generating a cache set identifier to access the cache structure, the identifier being generated by combining a seed value generated by the module for generating seed values and predetermined bits of an address to access a main memory associated to the cache structure.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: July 19, 2016
    Assignee: BARCELONA SUPERCOMPUTING CENTER
    Inventors: Jaime Abella Ferrer, Eduardo Quiñones Moreno, Francisco Javier Cazorla Almeida
  • Publication number: 20140082284
    Abstract: The present disclosure relates to a device for controlling the access to a cache structure comprising multiple cache sets during the execution of at least one computer program, the device comprising a module for generating seed values during the execution of the at least one computer program; a parametric hash function module for generating a cache set identifier to access the cache structure, the identifier being generated by combining a seed value generated by the module for generating seed values and predetermined bits of an address to access a main memory associated to the cache structure.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
    Inventors: JAIME ABELLA FERRER, EDUARDO QUIÑONES MORENO, FRANCISCO JAVIER CAZORLA ALMEIDA
  • Publication number: 20070023848
    Abstract: A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
    Type: Application
    Filed: October 4, 2006
    Publication date: February 1, 2007
    Inventors: Kurt Steiner, Gerald Gibson, Eduardo Quinones