Patents by Inventor Eduardo Viegas
Eduardo Viegas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10389364Abstract: In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit is coupled to the oscillator core circuit for calibrating the gain control signal to a startup value based on oscillations reaching a first threshold during a startup state, and calibrating the gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of the startup state and before entering a steady state. The first threshold is higher than the second threshold. The dynamic gain control circuit operates the oscillator core circuit during the steady state using the steady-state value.Type: GrantFiled: March 28, 2017Date of Patent: August 20, 2019Assignee: SILICON LABORATORIES INC.Inventor: Eduardo Viegas
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Publication number: 20170201258Abstract: In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit is coupled to the oscillator core circuit for calibrating the gain control signal to a startup value based on oscillations reaching a first threshold during a startup state, and calibrating the gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of the startup state and before entering a steady state. The first threshold is higher than the second threshold. The dynamic gain control circuit operates the oscillator core circuit during the steady state using the steady-state value.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Applicant: Silicon Laboratories Inc.Inventor: Eduardo Viegas
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Patent number: 9647670Abstract: In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit provides the gain control signal to set an absolute value of the gain to a first level during a startup state, and changes the gain control signal to reduce the absolute value of the gain to a second level lower than the first level after the first clock signal has reached a steady state.Type: GrantFiled: September 15, 2015Date of Patent: May 9, 2017Assignee: SILICON LABORATORIES INC.Inventor: Eduardo Viegas
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Publication number: 20170077931Abstract: In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit provides the gain control signal to set an absolute value of the gain to a first level during a startup state, and changes the gain control signal to reduce the absolute value of the gain to a second level lower than the first level after the first clock signal has reached a steady state.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Applicant: SILICON LABORATORIES INC.Inventor: Eduardo Viegas
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Patent number: 9020165Abstract: Pop/clock noise reduction circuitry is disclosed for audio output circuitry. After audio output circuitry is enabled, reference voltage generator circuitry is then enabled to produce a reference voltage that ramps from a first voltage level to a second voltage level at a smooth rate. The ramping reference voltage is applied to the input of the audio output circuitry to reduce or prevent pop/click noise for the audio output circuitry. Further, negative offset control circuitry can also be used to provide a negative offset input to the audio output circuitry to remove initial step-up voltage levels that may exist at operational power-up for the audio output circuitry. Still further, current control circuitry can also be used that limits the available current flowing to the output node for the audio output circuitry, thereby further reducing and/or preventing potential pop/click noise in the audio output signals.Type: GrantFiled: October 9, 2012Date of Patent: April 28, 2015Assignee: Silicon Laboratories Inc.Inventor: Eduardo Viegas
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Publication number: 20140098974Abstract: Pop/clock noise reduction circuitry is disclosed for audio output circuitry. After audio output circuitry is enabled, reference voltage generator circuitry is then enabled to produce a reference voltage that ramps from a first voltage level to a second voltage level at a smooth rate. The ramping reference voltage is applied to the input of the audio output circuitry to reduce or prevent pop/click noise for the audio output circuitry. Further, negative offset control circuitry can also be used to provide a negative offset input to the audio output circuitry to remove initial step-up voltage levels that may exist at operational power-up for the audio output circuitry. Still further, current control circuitry can also be used that limits the available current flowing to the output node for the audio output circuitry, thereby further reducing and/or preventing potential pop/click noise in the audio output signals.Type: ApplicationFiled: October 9, 2012Publication date: April 10, 2014Applicant: SILICON LABORATORIES INC.Inventor: Eduardo Viegas
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Patent number: 8446186Abstract: In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.Type: GrantFiled: June 7, 2010Date of Patent: May 21, 2013Assignee: Silicon Laboratories Inc.Inventors: John M. Khoury, Eduardo Viegas
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Patent number: 8433028Abstract: In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.Type: GrantFiled: June 7, 2010Date of Patent: April 30, 2013Assignee: Silicon Laboratories Inc.Inventors: John M. Khoury, Eduardo Viegas, Richard Beale
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Publication number: 20130002304Abstract: Techniques are disclosed relating to tracking edges of a signal of a buffer circuit. In one embodiment, an apparatus is disclosed that includes a sampling circuit configured to sample a pulse width modulation (PWM) signal to generate a threshold voltage based on an average of the high and low voltage levels of the PWM signal and to provide the threshold voltage to an input of a comparator of the apparatus. The comparator is configured receive the threshold voltage and the PWM voltage and perform edge detection on the threshold voltage and PWM signal.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Inventors: Pio Balmelli, Eduardo Viegas
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Publication number: 20110298505Abstract: In an embodiment, a circuit includes a buffer circuit including a buffer input and an output terminal and a latency locked loop (LLL) circuit. The LLL circuit includes a signal input for receiving an input signal, a feedback input coupled to the output terminal, and a signal output coupled to the buffer input. The LLL circuit is configured to control a propagation delay between the signal input and the signal output to produce a substantially constant total delay from the signal input to the output terminal.Type: ApplicationFiled: June 7, 2010Publication date: December 8, 2011Applicant: SILICON LABORATORIES, INC.Inventors: John M. Khoury, Eduardo Viegas, Richard Beale
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Publication number: 20110298509Abstract: In an embodiment, a device includes a buffer circuit with first and second buffer outputs and a latency locked loop (LLL) circuit. The LLL circuit includes first and second LLL inputs for receiving first and second input signals and includes at least one shared component that is time shared. The at least one shared component is configured to measure edge timing errors in output signals on the first and second buffer outputs relative to the first and second inputs signals and to generate delay adjustment signals to adjust timing of edge transitions within the first and second input signals provided to the buffer circuit to control a total propagation delay from the first and second LLL inputs to the first and second buffer outputs.Type: ApplicationFiled: June 7, 2010Publication date: December 8, 2011Applicant: SILICON LABORATORIES, INC.Inventors: John M. Khoury, Eduardo Viegas