Abstract: A slave device communicates with a host system via a host communications bus. The host system includes one processor that can act as bus master and send access requests for slave resources on the slave device via the communications bus. The slave device platform includes a memory management unit, a programmable central processor and one slave resource. The memory management unit acts as an address translating device, and accepts requests with virtual addresses from a master device on the host system, translates the virtual addresses used in the access request to the “internal” physical addresses of the slave's resources and forwards the accesses to the appropriate physical resource. When an address miss occurs in the memory management unit, it passes the handling of the access request over to the controlling CPU which executes software to then resolve the address miss and handle the access request.

Abstract: The early depth test stages 4, 13 of a graphics processing pipeline 1 are configured to broadcast information 9, 10, 11, 14 about fragments, etc., that pass those early depth tests to other stages 3, 4, 6, 12 in the pipeline. The other stages in the pipeline then use the early depth test pass information to determine if the processing of any fragments that they are currently processing can be stopped.

Abstract: The early depth test stages 4, 13 of a graphics processing pipeline 1 are configured to broadcast information 9, 10, 11, 14 about fragments, etc., that pass those early depth tests to other stages 3, 4, 6, 12 in the pipeline. The other stages in the pipeline then use the early depth test pass information to determine if the processing of any fragments that they are currently processing can be stopped.

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail (52) is not present in the local memory of the graphics processing system (53), the virtual texture lookup process loops back to try to sample the texture at an increased level of detail (55), and so on, until texture data that can be used is found in the local memory of the graphics processing system (53). This allows the texturing operation to proceed using texture data for the texel positions in question from a higher level (less detailed) mipmap in place of the originally desired texture data.

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch.

Abstract: A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.

Abstract: A graphic rendering pipeline has a number of different rendering units and receives fragments for rendering. A renderer stated word cache is used to store rendering state data to be used to configure the rendering units when they render a fragment. Each rendering unit includes a functional block which carries out a rendering operation on a received fragment and a renderer state word interface that can be used to look up the required rendering state data from the renderer state word cache. Each fragment is provided to the rendering pipeline with fragment data that indicates, inter alia, a fragment index, a renderer state word index, and other fragment data that is necessary to render the fragment. When a rendering unit of the rendering pipeline receives a fragment to be rendered, it firstly uses the renderer state word index associated with the fragment to look-up, using its renderer state word interface, the relevant rendering state data from the renderer state word cache.

Abstract: A distribution medium (20) for providing an application to a host system (4) includes an interface element (21) for interfacing with the host (4), a memory or storage module (22) that stores application code representing the application and a hardware element (23). The hardware element (23) directly accesses application content stored in the memory (22), processes that application content to transform it to another form, and then provides the transformed content to the host system (4).

Abstract: A slave device (20) communicates with a host system (21) via a host communications bus (22). The host system (21) includes one (or more) processing units that can act as bus masters and send access requests for slave resources on the slave device (20) via the communications bus (22). The slave device platform (20) includes a memory management unit (23), a programmable central processing unit (24) and one or more slave resources (25). The memory management unit (23) acts as an address translating device, and accepts requests with virtual addresses from the master device or devices on the host system (21), translates the virtual addresses used in the access requests to the “internal” physical addresses of the slave's resources and forwards the accesses of the appropriate physical resources (25).

Abstract: In a tile-based graphics processing system, when an overlay image is to be rendered onto an existing image, the existing tile data for the existing image from the frame buffer in the main memory is pre-loaded into the local colour buffer of the graphics processor (step 41). The overlay content is then rendered and used to modify the tile data stored in the colour buffer (step 44). When the data for a given sampling position stored in the tile buffer is modified as a result of the overlay image, a corresponding dirty bit for the tile region that the sampling position falls within is set (step 45). Then, when all the rendering for the tile has been completed, the dirty bits are examined to determine which regions of the tile have been modified (step 46). The modified tile regions are written back to the output image in the frame buffer in the main memory (step 47), but any regions whose dirty bits have not been set are not written back to the frame buffer in the main memory.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and hence output to a frame buffer 54 of a display device 55 for display.

Abstract: A memory management arrangement includes a memory management unit, a cache memory and a queue arrangement. The queue is a first-in, first-out (FIFO) buffer which can queue failed memory access requests and return them as inputs to the memory management unit via the bus 5 for retrying through the memory management unit at a later time. If a memory access request sent to the memory management unit experiences a cache “miss”, instead of blocking memory access requests until the required address data has been loaded into the cache, the memory management unit operates to place the failed memory access request in the replay queue, and allows subsequent memory access requests to continue. The failed memory access requests in the queue are then continuously circulated through the memory management unit from the queue alternately with new memory access requests from other access initiators.

Abstract: A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of colour values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colours of the individual texture elements using that generated set of colours. As well as the individual texture data blocks, a header data block encoding a base set of colours is generated. This base colour set defines a set of colours that is used to generate the colours to be used when reproducing each individual encoded texture data block.

Abstract: A 3D graphics rendering pipeline is used to carry out data comparisons for motion estimation in video data encoding. Video data for the pixel block of the video frame currently being encoded is loaded into the output buffers of the rendering pipeline. The video data for the comparison pixel blocks from the reference video frame is stored as texture map values in the texture cache of the rendering pipeline. Once the sets of pixel data for comparison have been stored, the rendering pipeline is controlled to render a primitive having fragment positions and texture coordinates corresponding to the data values that it is desired to compare. As each fragment is rendered, the stored and rendered fragment data is compared by fragment compare unit and the determined differences in the data values are accumulated in an error term register.

Abstract: An array of texture data elements (texels) is subdivided into a plurality of 8×4 texture element blocks, each of which 8×4 texture element blocks encodes two 4×4 texture element sub-blocks 3, 4. Each encoded texture data block includes data indicating a method to be used to generate a set of color values to be used for the texture elements that the encoded data block represents, and data indicating a method to be used for generating the colors of the individual texture elements using that generated set of colors. As well as the individual texture data blocks, a header data block encoding a base set of colors is generated. This base color set defines a set of colors that is used to generate the colors to be used when reproducing each individual encoded texture data block.

Abstract: A windowing display using deferred drawing commands operates by processing the drawing commands that write to a tile 22 of a frame buffer 30 to form one or more new pixel values are stored within a tile memory 40. Dirty pixel data indicative of which pixels within the tile memory are dirty pixels storing new pixel values and which pixels within the tile memory are clean pixels not storing new pixel values is also formed. In dependence upon the dirty pixel data, the new pixel value stored within the tile memory are written to the frame buffer memory. Pixels stored within the frame buffer memory corresponding to clean pixels within the tile memory remain unaltered as they are not written.

Abstract: A graphics processing platform includes a rasteriser 50 that receives primitives representing an image to be displayed for processing. The rasteriser 50 determines which sets of sampling points of the image include sampling points that are covered by a given primitive, and then generates a fragment for rendering for each set of sampling points found to include a sampling point that is covered by the primitive and passes those fragments to a renderer 51 for rendering. The renderer 51 carries out rendering operations on the fragments that it receives, and stores the rendered fragment data in tile buffers 52. The rendered fragment data is stored in multiple copies in the appropriate sample positions in the tile buffers 52, so as to provide a separate set of fragment data for each individual sample position taken of the image. The data from the tile buffers 52 is input to a downsampling unit 53, and thence output to a frame buffer 54 of a display device 55 for display.

Abstract: A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access requests from the accelerator processor are received by a memory request switching circuitry which is responsive to a signal from the accelerator processor to direct the memory access request either via coherency control circuit or directly to the further memory.