Patents by Inventor Edvin Cetegen

Edvin Cetegen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210305132
    Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Omkar KARHADE, Digvijay RAORANE, Sairam AGRAHARAM, Nitin DESHPANDE, Mitul MODI, Manish DUBEY, Edvin CETEGEN
  • Publication number: 20210249322
    Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.
    Type: Application
    Filed: February 11, 2020
    Publication date: August 12, 2021
    Applicant: Intel Corporation
    Inventors: Ziyin Lin, Vipul Mehta, Wei Li, Edvin Cetegen, Xavier Brun, Yang Guo, Soud Choudhury, Shan Zhong, Christopher Rumer, Nai-Yuan Liu, Ifeanyi Okafor, Hsin-Wei Wang
  • Publication number: 20210242107
    Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to a substrate that includes a first region to be coupled with a die, and a second region separate and distinct from the first region that has a lower thermal conductivity than the first region, where the second region is to thermally insulate the first region when the die is coupled to the first region. The thermal insulation of the second region may be used during a TCB process to increase the quality of each of the interconnects of the die by promoting a higher temperature at the connection points to facilitate full melting of solder.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Mitul MODI, Nicholas NEAL
  • Publication number: 20210195798
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.
    Type: Application
    Filed: December 20, 2019
    Publication date: June 24, 2021
    Inventors: Nicholas NEAL, Nicholas S. HAEHN, Je-Young CHANG, Kyle ARRINGTON, Aaron MCCANN, Edvin CETEGEN, Ravindranath V. MAHAJAN, Robert L. SANKMAN, Ken P. HACKENBERG, Sergio A. CHAN ARGUEDAS
  • Publication number: 20210104490
    Abstract: Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Wei LI, Edvin CETEGEN, Nicholas S. HAEHN, Ram S. VISWANATH, Nicholas NEAL, Mitul MODI
  • Publication number: 20210066162
    Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Sergio A. CHAN ARGUEDAS, Nicholas S. HAEHN, Edvin CETEGEN, Nicholas NEAL, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON, Vipul MEHTA
  • Publication number: 20210035921
    Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
  • Publication number: 20210028084
    Abstract: Embodiments may relate to a microelectronic package that includes a die, a thermal interface material (TIM) coupled with the die, and an integrated heat spreader (IHS) coupled with the TIM. The IHS may include a feature with a non-uniform cross-sectional profile that includes a thin point and a thick point as measured in a direction perpendicular to a face of the die to which the TIM is coupled. Other embodiments may be described or claimed.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 28, 2021
    Applicant: Intel Corporation
    Inventors: Sergio Antonio Chan Arguedas, Edvin Cetegen, Baris Bicen, Aravindha R. Antoniswamy
  • Publication number: 20210020532
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Edvin CETEGEN, Nicholas NEAL, Sergio CHAN ARGUEDAS
  • Publication number: 20210020531
    Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Edvin CETEGEN, Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Nicholas NEAL, Sergio CHAN ARGUEDAS, Vipul MEHTA
  • Publication number: 20200402920
    Abstract: An integrated circuit package may be formed comprising a substrate that includes a mold material layer and a signal routing layer, wherein the mold material layer comprises at least one bridge and at least one foam structure embedded in a mold material. In one embodiment, the substrate may include the mold material of the mold material layer filling at least a portion of cells within the foam structure. In a further embodiment, at least two integrated circuit devices may be attached to the substrate, such that the bridge provides device-to-device interconnection between the at least two integrated circuit devices. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board.
    Type: Application
    Filed: June 18, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Mufei Yu, Gang Duan, Edvin Cetegen, Baris Bicen, Rahul Manepalli
  • Publication number: 20200273768
    Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
  • Publication number: 20200273775
    Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Inventors: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
  • Publication number: 20200273772
    Abstract: An apparatus is provided which comprises: a package substrate, an integrated circuit device coupled to a surface of the package substrate, a first material on the surface of the package substrate, the first material contacting one or more lateral sides of the integrated circuit device, the first material extending at least to a surface of the integrated circuit device opposite the package substrate, two or more separate fins over a surface of the integrated circuit device, the two or more fins comprising a second material having a different composition than the first material, and a third material having a different composition than the second material, the third material over the surface of the integrated circuit device and between the two or more fins. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Aastha Uppal, Omkar Karhade, Ram Viswanath, Je-Young Chang, Weihua Tang, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Kumar Singh
  • Publication number: 20200273811
    Abstract: IC package including a material preform comprising graphite. The material preform may have a thermal conductivity higher than that of other materials in the package and may therefore mitigate the formation of hot spots within an IC die during device operation. The preform may have high electrical conductivity suitable for EMI shielding. The preform may comprise a graphite sheet that can be adhered to a package assembly with an electrically conductive adhesive, applied, for example over an IC die surface and a surrounding package dielectric material. Electrical interconnects of the package may be coupled to the graphite sheet as an EMI shield. The package preform may be grounded to a reference potential through electrical interconnects of the package, which may be further coupled to a system-level ground plane. System-level thermal solutions may interface with the package-level graphite sheet.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Debendra Mallik, Mitul Modi, Sanka Ganesan, Edvin Cetegen, Omkar Karhade, Ravindranath Mahajan, James C. Matayabas, Jr., Jan Krajniak, Kumar Singh, Aastha Uppal
  • Publication number: 20200227332
    Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.
    Type: Application
    Filed: January 10, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Kumar Abhishek Singh, Omkar Karhade, Nitin Deshpande, Mitul Modi, Edvin Cetegen, Aastha Uppal, Debendra Mallik, Sanka Ganesan, Yiqun Bai, Jan Krajniak, Manish Dubey, Ravindranath Mahajan, Ram Viswanath, James C. Matayabas, JR.
  • Publication number: 20200203240
    Abstract: An integrated circuit assembly including a substrate having a surface including at least one area including contact points operable for connection with an integrated circuit die; and at least one ring surrounding the at least one area, the at least one ring including an electrically conductive material. A method of forming an integrated circuit assembly including forming a plurality of electrically conductive rings around a periphery of a die area of a substrate selected for attachment of at least one integrated circuit die, wherein the plurality of rings are formed one inside the other; and forming a plurality of contact points in the die area.
    Type: Application
    Filed: June 30, 2017
    Publication date: June 25, 2020
    Inventors: Nicholas S. HAEHN, Edvin CETEGEN, Shankar DEVASENATHIPATHY
  • Publication number: 20200146183
    Abstract: A conformable heat sink interface for an integrated circuit package comprises a mounting plate having a first surface and a deformable membrane having a portion bonded to a second surface of the plate. A cavity is between the second surface of the plate and the deformable membrane. A flowable heat transfer medium is within the cavity. The flowable heat transfer medium has a thermal conductivity of not less than 30 W/m K. The deformable membrane is to conform to a three-dimensional shape of an IC package and the mounting plate has a second surface that is to be adjacent to a heat sink base.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 7, 2020
    Applicant: Intel Corporation
    Inventors: Kelly Lofgreen, Joseph Petrini, Todd Coons, Christopher Wade Ackerman, Edvin Cetegen, Yang Jiao, Michael Rutigliano, Kuang Liu
  • Publication number: 20200098661
    Abstract: Embodiments include an electronic system and methods of forming an electronic system. In an embodiment, the electronic system may include a package substrate and a die coupled to the package substrate. In an embodiment, the electronic system may also include an integrated heat spreader (IHS) that is coupled to the package substrate. In an embodiment the electronic system may further comprise a thermal interface pad between the IHS and the die. In an embodiment the die is thermally coupled to the IHS by a liquid metal thermal interface material (TIM) that contacts the thermal interface pad.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Kelly LOFGREEN, Chia-Pin CHIU, Joseph PETRINI, Edvin CETEGEN, Betsegaw GEBREHIWOT, Feras EID
  • Publication number: 20200043894
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 6, 2020
    Inventors: George VAKANAS, Aastha UPPAL, Shereen ELHALAWATY, Aaron MCCANN, Edvin CETEGEN, Tannaz HARIRCHIAN, Saikumar JAYARAMAN