Patents by Inventor Edvin Paparisto
Edvin Paparisto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9569354Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.Type: GrantFiled: August 2, 2013Date of Patent: February 14, 2017Assignee: Infineon Technologies AGInventors: Ulrich Backhausen, Thomas Kern, Thomas Nirschl, Jens Rosenbusch, Xiangting Bi, Edvin Paparisto
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Patent number: 9389999Abstract: The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.Type: GrantFiled: August 17, 2012Date of Patent: July 12, 2016Assignee: Infineon Technologies AGInventors: Thomas Kern, Jens Rosenbusch, Ulrich Backhausen, Edvin Paparisto, Thomas Nirschl
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Patent number: 9251864Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.Type: GrantFiled: September 6, 2012Date of Patent: February 2, 2016Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Thomas Kern
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Patent number: 9190149Abstract: Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.Type: GrantFiled: August 24, 2012Date of Patent: November 17, 2015Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Christian Peters
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Patent number: 9032140Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.Type: GrantFiled: January 28, 2013Date of Patent: May 12, 2015Assignee: Infineon Technologies AGInventors: Wolf Allers, Jan Otterstedt, Mihail Jefremow, Edvin Paparisto, Leonardo Castro
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Publication number: 20150039805Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system to emulate an electrically erasable programmable read-only memory, and a method to emulate an electrically erasable programmable read-only memory. According to an embodiment of the disclosure, a system to emulate an electrically erasable programmable read-only memory is provided, the system including a first memory section and a second memory section, wherein the first memory section comprises a plurality of storage locations configured to store data partitioned into a plurality of data segments and wherein the second memory section is configured to store information mapping a physical address of a data segment stored in the first memory section to a logical address of the data segment.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Inventors: Ulrich Backhausen, Thomas Kern, Thomas Nirschl, Jens Rosenbusch, Xiangting Bi, Edvin Paparisto
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Publication number: 20140215124Abstract: The disclosure relates to an electronic memory system, and more specifically, to a system for adaptive bit rate programming of a memory device, and a method for adaptive bit rate programming of a memory device. According to an embodiment, a system for adaptive bit rate programming of a memory device including a plurality of memory cells is provided, wherein the memory cells are configured to be electrically programmable by application of a current supplied by a current source, the system including selection devices for selecting memory cells for programming based on availability of current from the current source.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: Infineon Technologies AGInventors: Wolf Allers, Jan Otterstedt, Mihail Jefremow, Edvin Paparisto, Leonardo Castro
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Publication number: 20140064011Abstract: The invention relates to an electronic memory system, and more specifically, to a system for providing voltage supply protection in a memory device, and a method for providing voltage supply protection in a memory device. According to an embodiment, a system for providing voltage supply protection in a memory device is provided, the system including a memory array including a plurality of memory cells arranged in a plurality of groups of memory cells, and a plurality of current limiting elements, wherein each group of memory cells is associated with at least one current limiting element.Type: ApplicationFiled: September 6, 2012Publication date: March 6, 2014Applicant: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Thomas Kern
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Publication number: 20140056079Abstract: Embodiments relate to systems and methods including a step of switching between two or more erase operations and/or two or more write operations for erasing of and/or writing to least one memory cell of a nonvolatile memory enabling to select a most suitable erase and/or write operation for a particular erase and/or write operation within the memory.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: Infineon Technologies AGInventors: Jan Otterstedt, Wolf Allers, Mihail Jefremow, Edvin Paparisto, Leonardo Castro, Christian Peters
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Publication number: 20140052896Abstract: The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: Infineon Technologies AGInventors: Thomas Kern, Jens Rosenbusch, Ulrich Backhausen, Edvin Paparisto, Thomas Nirschl
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Patent number: 7675781Abstract: A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.Type: GrantFiled: December 1, 2006Date of Patent: March 9, 2010Assignee: Infineon Technologies AGInventors: Christoph Deml, Edvin Paparisto
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Patent number: 7643341Abstract: An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as read line, or the same line serves both as delete line and as read line. The memory cell arrangement includes at least one delete memory sector and at least one read memory section. The number of memory cells of at least one delete memory sector does not concur with the number of memory cells of at least one read memory sector.Type: GrantFiled: February 28, 2007Date of Patent: January 5, 2010Assignee: Infineon Technologies AGInventors: Christoph Deml, Thomas Liebermann, Edvin Paparisto
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Patent number: 7548474Abstract: A method for reading out a memory cell, and a device to be used for reading out a memory cell. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value, wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.Type: GrantFiled: June 1, 2006Date of Patent: June 16, 2009Assignee: Infineon Technologies AGInventors: Edvin Paparisto, Stephan Rogl
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Publication number: 20080133849Abstract: A memory device, including a non-volatile memory device, a method for operating a memory device, and an apparatus for use with a memory device is disclosed. In one embodiment, the memory device includes at least one evaluation circuit for amplifying a signal resulting from the reading of a memory cell, and a device for precharging an output of the evaluation circuit to a predetermined voltage level.Type: ApplicationFiled: December 1, 2006Publication date: June 5, 2008Inventors: Christoph Deml, Edvin Paparisto
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Patent number: 7379339Abstract: The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.Type: GrantFiled: November 16, 2005Date of Patent: May 27, 2008Assignee: Infineon Technologies AGInventors: Edvin Paparisto, Stephan Rogl
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Publication number: 20070223284Abstract: An integrated circuit having a memory arrangement is disclosed. In one embodiment, the memory arrangement includes a plurality of memory cells, a delete line for deleting the memory cells, and a read line for reading out the memory cells. There are either provided separate lines as delete line and as read line, or the same line serves both as delete line and as read line. The memory cell arrangement includes at least one delete memory sector and at least one read memory section. The number of memory cells of at least one delete memory sector does not concur with the number of memory cells of at least one read memory sector.Type: ApplicationFiled: February 28, 2007Publication date: September 27, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Christoph Deml, Thomas Liebermann, Edvin Paparisto
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Patent number: 7236403Abstract: Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).Type: GrantFiled: December 7, 2004Date of Patent: June 26, 2007Assignee: Infineon Technologies AGInventors: Christoph Deml, Thomas Liebermann, Edvin Paparisto, Stephan Rogl
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Publication number: 20060280008Abstract: A method for reading out a memory cell, and a device to be used for reading out a memory cell is disclosed. In one embodiment, the device includes a first circuit and a second circuit for regulating a voltage present at a line that is adapted to be connected with the memory cell to a predetermined value (Uref), wherein said first circuit includes a switching element, and wherein said first circuit is configured such that said switching element is switched on during a first regulating phase and is switched off during a second regulating phase.Type: ApplicationFiled: June 1, 2006Publication date: December 14, 2006Inventors: Edvin Paparisto, Stephan Rogl
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Publication number: 20060126388Abstract: The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.Type: ApplicationFiled: November 16, 2005Publication date: June 15, 2006Applicant: INFINEON TECHNOLOGIES AGInventors: Edvin Paparisto, Stephan Rogl
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Publication number: 20050128813Abstract: Precharge arrangement for read access for integrated nonvolatile memories having at least one memory cell (2), at least one source line (8), at least one bit line (9), at least one sense amplifier (3) and at least one precharge potential, the bit line (9) continuously having the precharge potential in a deselected state of the bit line (9), and the source line (8) having a predetermined reference potential, in particular a ground potential (10), in a selected state of the bit line (9).Type: ApplicationFiled: December 7, 2004Publication date: June 16, 2005Inventors: Christoph Deml, Thomas Liebermann, Edvin Paparisto, Stephan Rogl