Abstract: Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.

Abstract: Apparatuses, systems, methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, an SMS prefetch engine uses trigger-to-trigger stride detection to promote training table entries to pattern history table (PHT) entries and to drive spatially related prefetches in more distant regions. In another aspect, an SMS prefetch engine maintains a blacklist of program counter (PC) values to not use as trigger values. In yet another aspect, an SMS prefetch engine uses hashed values of certain fields, such as the trigger PC, in entries of, e.g., filter tables, training tables, and PHTs, as index values for the table.

Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.

Abstract: Apparatuses, systems, methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, an SMS prefetch engine uses trigger-to-trigger stride detection to promote training table entries to pattern history table (PHT) entries and to drive spatially related prefetches in more distant regions. In another aspect, an SMS prefetch engine maintains a blacklist of program counter (PC) values to not use as trigger values. In yet another aspect, an SMS prefetch engine uses hashed values of certain fields, such as the trigger PC, in entries of, e.g., filter tables, training tables, and PHTs, as index values for the table.

Abstract: Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.

Abstract: According to one general aspect, an apparatus may include a cache pre-fetcher configured to predict data to be retrieved from a memory system. The cache pre-fetcher may include a pattern predictor circuit and a confirmation queue circuit. The pattern predictor circuit may be configured to predict a series of memory addresses to be pre-fetched from the memory system. The confirmation queue circuit may be configured to: maintain a windowed confirmation queue of predicted memory addresses, compare a requested memory address against the predicted memory addresses, and, if the requested memory address is included in the predicted memory addresses, indicate that a successful pre-fetch has occurred.

Abstract: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.

Abstract: An apparatus and method are provided for renaming a logical register for which bit accesses of varying lengths are permitted, such as a predicate register. Rename logic supports renaming for both partial-bit accesses and bulk-bit accesses to bits of the register. Rename logic utilizes a rename map table associated with the logical register to be renamed and also includes a plurality of physical rename registers. They physical rename registers include a set of skinny physical rename registers to be used for renaming for partial-bit writes. The physical rename registers also include a set of fat physical rename registers to be used for renaming for bulk-bit writes. Additional sizes of physical rename registers may also be employed. The entries of the single physical rename map table may point to either fat or skinny physical rename registers.

Abstract: A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.

Abstract: A register renaming technique for dynamic multithreading. One disclosed embodiment includes a register map to store up to M×N values to map M registers for N threads. A set of N values, one per thread, and a set of state bits is associated with each of the M registers. Each set of state bits indicates which of the N values per register are valid and whether ones of the N sets of values have been written by a dynamic execution thread. In response to termination of a dynamic execution thread, recovery logic may update state bits associated with ones of the M registers that were written to during dynamic execution.

Abstract: A method to handle data dependencies in a pipelined computer system is disclosed. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by correlating a busy condition of a computer instruction to each register.

Abstract: A mechanism, which supports predictive register cache allocation and entry, uses a counter look-up table to determine the potential significances of physical register references.

Abstract: A method and apparatus are provided for providing ready information to a scheduler. Dependence information is maintained in a relatively small map table, with potential loss of information when dependence information exceeds available space in the map table. Ready instructions are maintained, as space allows, in a select queue. Tags for scheduled instructions are maintained in a lookup queue, and dependency information for the scheduled instruction is maintained in an update queue, as space allows. Ready information for instructions in a scheduling window is updated based upon the information in the update queue. Loss of instruction information may occur, due to space limitations, at the map table, lookup queue, update queue, and/or select queue. Scheduling of lost instructions is handled by a lossy instruction handler.

Abstract: Embodiments of an apparatus, method, and system provide for no-operation instruction (“NOP”) folding such that information regarding the presence of a NOP instruction in the instruction stream is folded into a buffer entry for another instruction. Information regarding a target NOP instruction is thus maintained in a buffer entry associated with an instruction other than the target NOP instruction. For at least one embodiment, NOP information is folded into entries of a re-order buffer.

Abstract: A technique to use available register cache resources if register file resources are unavailable. Embodiments of the invention pertain to a register cache writeback algorithm for storing writeback data to a register cache if register file write ports or space is unavailable.

Abstract: After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is not read in the next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used to update a history table. The history table stores information to indicate if an instruction is a slowable instruction or a non-slowable instruction. When the instruction address of the instruction is encountered at a second time, the history table is used to determine if the instruction is slowable or non-slowable.