Abstract: A method for determining the net value of an information technology application or portfolio of applications. User value contributions for the application are developed by calculating internal user costs and external costs, following which, breakouts of the organizational IT budget as well as staffing costs and resources are carried out. From the data thus developed, total application value is determined in conjunction with an uplift factor as applied to a base application value. Factors representing unavailability, potential total loss, and inflexibility are derived and subtracted from the total application value along with a subtraction of a total IT budget to achieve a net application value corresponding with the value of the analyzed application.

Abstract: Method and system for assessing and quantifying the business value of an information technology application or set of applications, particularly as those application or applications are subjected to a proposed change or variation. The method includes steps wherein a base application value is derived, following which a business experience based coefficient or factor is derived and, by using that coefficient or factor, the base application value is uplifted to provide an actual application value for an application or applications. A potential business value is derived by operating on the actual application value with a value representing the perceived value of an enablement attribute construct corresponding with the noted change to be applied. The ultimately sought net business value is derived for an application by removing the operational cost of the application from the potential business value.

Abstract: An apparatus provides a sequence detected signal indicating that a synchronization sequence occurring at regular intervals in a stream of data has occurred or should have occurred. The apparatus includes logic for detecting the synchronization sequence, logic responsive to the detection logic for producing the sequence detected signal when the detection logic detects the sequence, and logic for producing the sequence detected signal at a fixed time after the synchronization sequence should have occurred. If the synchronization sequence did occur, the apparatus thus produces two sequence detected signals; however, the device receiving the sequence detected signal responds to the first sequence detected signal and ignores the second. If the synchronization sequence did not occur, the device receiving the sequence detected signal responds to the sequence detected signal produced by the logic responsive to the timing apparatus.

Abstract: Disk drive control apparatus for controlling operation of a disk drive. The disk drive control apparatus has hierarchical control and includes control apparatus for controlling other components of the disk drive control apparatus, a controller interface receiving a bus connecting the disk drive control apparatus to a controller, a read-write processor for processing data received from or read to the disk, and data transfer apparatus for transferring data alternatively between the bus connected to the controller interface and the read-write processor, between the bus and the control apparatus, and between the read-write processor and the control apparatus. The control apparatus receives operational instructions from the controller via the bus, and responds to the operational instructions by providing internal instructions for the data transfer apparatus and the read-write processor.

Abstract: Logic circuitry for use in electrical apparatus for providing an interrupt signal to a controller when there is a power failure in the electrical apparatus. The logic circuitry is connected to a bus from the controller. When the logic circuitry receives a power failure signal, it sets an interrupt state register and provides an interrupt signal on the bus as long as the interrupt state register is set. If the power failure signal no longer indicates a power failure, the logic circuitry responds to a signal from the controller indicating that the interrupt has been received by resetting the interrupt state register, thereby ending the interrupt. However, if the power failure signal is still active, the logic circuitry will not reset the interrupt state register in response to the signal from the controller.

Abstract: Digital encoding and decoding apparatus for encoding data codes to produce disk codes and decoding disk codes to produce data codes. In the encoding and decoding operations performed by the apparatus, the output consists of a code and a state which are produced from a current input code, a next input code, and the state code produced by the last operation. The apparatus consists of a PROM and a state code register for retaining the state code produced by the last encoding or decoding operation. The registers in the prom contain two sets of code-status words. Each code-status word in one set contains a disk code and a state code which are the result of an encoding operation; each code-status word in the other set represents a data code and a state code which are the result of a decoding operation. The state code register receives the bits of the code-status word which contain the state code.

Abstract: A method useful in a disk drive for diagnosing malfunctions in the path by which data codes are encoded into disk codes and written to the disk and by which disk codes are read from the disk and decoded into data codes. The disk drive in which the method is used includes control apparatus having a memory for controlling operation of the disk drive, a read-write processor for translating data codes to disk codes and vice-versa, and data transfer means including a memory for transferring data codes internally in the disk drive. In the method, a copy of a test pattern stored in the memory belonging to the control apparatus is made and provided to the memory in the data transfer means. It is provided from then to the read-write processor, which translates the data codes in the copy to disk codes and writes them to a diagnostic track on the disk. The disk codes are then read from the diagnostic track and translated by the read-write processor.

Abstract: A digital data bus system for connecting a controller and a disk drive. Data on the disk is stored in track sectors containing a header and data. The controller includes a high-speed processor which performs a header compare operation comparing the values received from a header with the expected contents of the header and operations which determine when all of the data in a track sector has been transferred. The digital data bus system includes a bus for transferring data between the controller and the disk drive and a header-data mode bus for providing a header mode signal and a data mode signal from the controller to the disk drive. During an operation transferring data between the controller and the disk, the disk drive responds to the header mode signal by transferring a header to the controller.

Abstract: Apparatus in a disk drive connected by separate buses to two controllers for suspending the effect of a reserve instruction received from one controller when the other controller has already reserved the disk drive until the other controller releases the disk drive. The apparatus corresponding to each controller consists of suspended reserve logic and a register for retaining state indicating whether the controller has reserved the bus and state indicating whether the reserve operation has been suspended for the controller. The suspended reserve logic for a given controller receives inputs from the controller's bus, from the state stored in its register, and from the state in the suspended reserve apparatus for the other controller indicating whether that controller has reserved the disk drive. Outputs from the suspended reserve logic go to its register.

Abstract: Encoding-decoding apparatus having an internal data path for diagnostic use. The apparatus includes control apparatus for providing signals controlling operation of the encoding-decoding apparatus, an input device connected to a source of data to be encoded and a source of data to be decoded, an output device connected to a destination for the encoded data and a destination for the decoded data, and apparatus connected between the input device and the output and device for performing the encoding and decoding. A data path responsive to the control signals receives encoded data from the output device and provides it to the input device.