Abstract: A self-organizing list machine is provided for reordering items of a list in a manner that achieves both a constant and minimum time complexity. The self-organizing list machine comprises an array of symbol index generators, wherein (i) each symbol index generator has a unique location in the array between zero and N?1 inclusive, and (ii) N is the total number of unique symbols in a symbol alphabet.

Abstract: A self-organizing list machine is provided for reordering items of a list in a manner that achieves both a constant and minimum time complexity. The self-organizing list machine comprises an array of symbol index generators, wherein (i) each symbol index generator has a unique location in the array between zero and N?1 inclusive, and (ii) N is the total number of unique symbols in a symbol alphabet.

Abstract: Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.

Abstract: Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.

Abstract: Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth associated with running multiple hardware acceleration processes can be reduced by chaining multiple independent hardware acceleration operations within a circuit card assembly. Multiple independent hardware accelerators can be configured on a single circuit card assembly that is coupled to a computing device. The computing device can generate a playlist of hardware acceleration operations identifying hardware accelerators and associated accelerator options. A task management unit on the circuit card assembly receives the playlist and schedules the hardware acceleration operations such that multiple acceleration operations may be successively chained together without intervening data exchanges with the computing device.

Abstract: An enhanced ATM switch with CPU node interconnect functionality and peripheral interconnect functionality and network functionality. The ATM switch provides low latency transfer between computer nodes and performs input/output operations with peripherals through the ATM network. SCSI Fibre Channel protocol (FCP) commands are implemented according to ATM standards to provide communication with peripherals. A segmentation and reassembly (SAR) unit is provided for performing ATM segmentation and reassembly. The SAR includes functional units which allow direct connection of an application agent to the core of the switch once the cell characteristics are determined by the application agent and provides ATM cell translation to and from available kernel buffers. The transmission media in the ATM network comprises digital optical links. The enhanced ATM switch may also include a synchronous optical network (SONET) interface for providing SONET transmission over the digital optical links in the ATM network.

Abstract: A golf swing training device which is used by both amateur and professional golfers to develop and maintain a proper golf swing. The golf swing training device not only forces the user to maintain one swing plane, but also allows the golfer to imitate the hand movement used in a proper golf swing, as well as allowing for the full extension of the golfer's arms in the follow through. Additionally, the golf swing training device develops the proper muscle groups for golfing.