Abstract: A method determining LOD values for a geometric primitive, in accordance with one embodiment of the present invention, includes accessing a plurality of geometric parameters of a vertex. An LOD value for a vertex is calculated as a function of the plurality of parameters of the vertex in a setup module. In a raster module an LOD value for a pixel is interpolated as a function of the LOD value of the pixel corresponding to the vertex and a view distance of the non-vertex pixel.

Abstract: A method and system for computing pixel parameters is disclosed. In one embodiment, the rasterizing of a geometric primitive comprising a plurality of vertices wherein each vertex comprises a respective color value, is performed by a rasterization module of a graphics pipeline. The rasterizing includes interpolating a respective color value for each pixel of the geometric primitive, wherein the respective color value is of a first bit width. The rasterizing also includes transforming the respective color value to a second bit width to produce a respective transformed color value for each pixel. Additionally, the rasterizing includes altering the respective transformed color value using a screen-location based dither table to produce a dithered transformed color value for each pixel. After the rasterizing, propagating the respective dithered transformed color value of each pixel to downstream modules of the graphics pipeline is performed.

Abstract: Embodiments for programming a graphics pipeline, and modules within the graphics pipeline, are detailed herein. Several of these embodiments utilize offset registers associated with the instruction tables for the modules within the pipeline. The offset register serves as a pointer to locations in the instruction table, which allows instructions to be written to be instruction table, without requiring that the shader programs have explicit addresses. One embodiment describes a method of programming a graphics pipeline. This method involves accessing the shader program stored in memory. A shader instruction is generated from this shader program, and loaded into an instruction table associated with a target module graphics pipeline. The shader instruction is loaded into the instruction table at the location indicated by an offset register.

Abstract: An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.

Abstract: Briefly, in accordance with one or more embodiments, a reconfigurable 3D graphics processor includes a pipeline configuration manager, a rasterizer, and a memory coupled to the triangle rasterizer. The pipeline configuration manager is capable of configuring the graphics processor to operate in a direct rasterizing mode or a tiling mode to process a sequence of drawing commands received from a processing unit.

Abstract: Briefly, in accordance with one or more embodiments of graphics processing, a current data signature is generated based at least in part on current input data, and the current data signature is compared with a prior cycle data signature. If the current data signature at least partially matches the prior cycle data signature, a prior cycle result may be fetched and processing of at least part of the current input data may be skipped.

Abstract: An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.

Abstract: Embodiments of the present invention pixel processing system and method provide convenient and efficient processing of pixel information. In one embodiment, quotient-remainder information associated with barycentric coordinate information indicating the location of a pixel is received. In one exemplary implementation quotient-remainder information is associated with barycentric coordinate information through the relationship c divided by dcdx, where c is the barycentric coordinate for a particular edge and dcdx is the derivative of the barycentric coordinate in the screen horizontal direction. The relationship of a pixel with respect to a primitive edge is determined based upon the quotient-remainder information. For example, a positive quotient can indicate a pixel is inside a triangle and a negative quotient can indicate a pixel is outside a triangle. Pixel processing such as shading is performed in accordance with the relationship of the pixel to the primitive.

Abstract: The boundary of a surface can be represented as a series of line segments. A number of polygons are successively superimposed onto the surface. The polygons utilize a common reference point and each of the polygons has an edge that coincides with one of the line segments. Coverage bits are associated with respective sample locations within a pixel. A value of a coverage bit is changed each time a sample location associated with the coverage bit is covered by one of the polygons. Final values of the coverage bits are buffered after all of the polygons have been processed. The values of the coverage bits can be used when the surface is subsequently rendered.

Abstract: A graphics processor is disclosed having a programmable Arithmetic Logic Unit (ALU) stage for processing pixel packets. Scalar arithmetic operations are performed in the ALUs to implement a graphics function.

Abstract: A computer-implemented graphics system that includes a rasterizer and a shader has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. In some instances, a primitive may cover only virtual sample locations and does not cover a real sample location. These instances can be identified in the coverage information sent from the rasterizer to the shader, so that the shader can determine whether or not it can write color information, depth information and/or stencil information for the real sample location to a framebuffer.

Abstract: A system and method for a row forwarding of pixel data in a 3-D graphics pipeline. Specifically, in one embodiment a data write unit capable of row forwarding in a graphics pipeline includes a first memory and logic. The first memory stores a plurality of rows of pixel information associated with a pixel. The plurality of rows of pixel information includes data related to surface characteristics of the pixel and includes a first row, e.g., a front row, and a second row, e.g., a rear row. A data write unit includes first logic for accessing a portion of the second row and for storing data accessed therein into a portion of the first row. The data write unit also comprises logic for recirculating the plurality of rows of pixel information to an upstream pipeline module for further processing thereof.

Abstract: A system, method and computer program product are provided for retrieving instructions from memory utilizing a texture module in a graphics pipeline. During use, an instruction request is sent to memory utilizing a texture module in a graphics pipeline. In response thereto, instructions are received from the memory in response to the instruction request utilizing the texture module in the graphics pipeline.

Abstract: A computer-implemented graphics system has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. A block of real sample locations can be selected to delineate and encompass a region containing a number of virtual sample locations. Pixel attribute values (e.g., z-depth or stencil values) associated with the block of selected real sample locations can be used to associate each virtual sample location within the region with one of the selected real sample locations. The virtual sample location assumes the pixel attribute value of the real sample location with which it is associated.

Abstract: In a raster unit of a graphics processor, a method for bounding region accumulation for graphics rendering. The method includes receiving a plurality of graphics primitives for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitives to generate a plurality pixels related to the graphics primitives and a plurality of respective bounding regions related to the graphics primitives. Upon receiving an accumulation start command, the bounding regions are accumulated in an accumulation register. The accumulation continues until an accumulation stop command is received. The operation results in an accumulated bounding region. Access to the accumulated bounding region is enabled to facilitate a subsequent graphics rendering operation.

Abstract: Data that includes an encoded version of sets of color component values for a block of texels is accessed. The encoded version includes a first set of color component values selected from a pre-encoded version of the sets and a second set of color component values selected from the pre-encoded version of the sets. The first set and the second set correspond to endpoints of a range of colors. The encoded version further includes index values associated with the texels. The first set and the second set and an index value associated with a texel are used to decode a third set of color component values that describes a color for the texel. The index value indicates how to determine the third set using the first set and the second set.

Abstract: A system and method for a data write unit in a 3-D graphics pipeline including generic cache memories. Specifically, in one embodiment a data write unit includes a first memory, a plurality of cache memories and a data write circuit. The first memory receives a pixel packet associated with a pixel. The pixel packet includes data related to surface characteristics of the pixel. The plurality of cache memories is coupled to the first memory for storing pixel information associated with a plurality of surface characteristics of a plurality of pixels. Each of the plurality of cache memories is programmably associated with a designated surface characteristic. The data write circuit is coupled to the first a memory and the plurality of cache memories. The data write circuit is operable under program control to obtain designated portions of the pixel packet for storage into the plurality of cache memories.

Abstract: A method and system for accessing texture data is disclosed. The method includes the step of storing a low resolution version of a block of texture data in a low latency memory and storing a high resolution version of the block of texture data in high latency memory. Upon a request for the high resolution version of the block of texture data, the high resolution version is fetched from the high latency memory to the low latency memory. The low resolution version is subsequently accessed from the low latency memory until the high resolution version is fetched into the low latency memory.

Abstract: Embodiments of the present invention include an arithmetic logic unit for use in a graphics pipeline. The arithmetic logic unit comprising a plurality of scalar arithmetic logic subunits wherein each subunit performs a resultant arithmetic logic operation in the form of [a*b “op” c*d] on a set of input operands a, b, c and d. The arithmetic logic unit also for produces a result based thereon wherein “op” represents a programmable operation and wherein further the resultant arithmetic logic operation is software programmable to implement a plurality of different graphics functions.

Abstract: An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register is coupled to the circuitry. The temporary register can receive a result of the operation. The temporary register allows a result generated using one set of pixel data to be used with a subsequent set of pixel data in the same ALU. The result of the operation can thus be used in a second operation with a second set of pixel data that resides in the pipeline register after the first set of pixel data.