Abstract: The present disclosure relates to systems, compositions and methods for modifying target nucleic acid sequences.

Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

Abstract: An amplifier having a Radio Frequency (RF) power level detector circuit for producing a control signal in accordance with a power level of an RF input signal. The control signal indicates whether the power level of the input signal is within a predetermined range of power levels greater than zero. A bias circuit is fed by the control signal, for producing a fixed bias voltage at a gate electrode of a field effect transistor (FET) to establish a predetermined quiescent current for the FET when the control signal indicates the power level of the RF input signal is within the predetermined range of power levels and to reduce the bias voltage to reduce the predetermined quiescent current when the control signal indicates the power level of the RF input signal is below the predetermined range of power levels.

Abstract: A microwave transmission line having a coplanar waveguide and a pair of conductive members, each one of the pair of conductive members having a proximal end disposed on a portion of a corresponding one of a pair of ground plane conductors of the coplanar waveguide and a distal end disposed over, and vertically spaced from, a region between a center conductor of the coplanar waveguide and a corresponding one of the pair of ground plane conductors of the coplanar waveguide. The distal ends are laterally separated from each other by a region disposed over the center conductor.

Abstract: A microwave transmission line having a coplanar waveguide and a pair of conductive members, each one of the pair of conductive members having a proximal end disposed on a portion of a corresponding one of a pair of ground plane conductors of the coplanar waveguide and a distal end disposed over, and vertically spaced from, a region between a center conductor of the coplanar waveguide and a corresponding one of the pair of ground plane conductors of the coplanar waveguide. The distal ends are laterally separated from each other by a region disposed over the center conductor.

Abstract: A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.

Abstract: A cpu-set type multiprocessor system allows a cpu of a cpu-set that has a hardware exception to disable itself and notify the system. The system assigns processes of the cpu-set that include the problem cpu to another cpu-set. The disabling of the problem cpu and transfer of the related processes to another cpu-set allows the system to failsoft so that other cpu-sets the multiprocessor system can continue to run and a recovery of the processes being run on the problem cpu-set occurs.