Patents by Inventor Edward Aung
Edward Aung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170155529Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: ApplicationFiled: December 12, 2016Publication date: June 1, 2017Inventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
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Patent number: 7684532Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: GrantFiled: April 25, 2007Date of Patent: March 23, 2010Assignee: Altera CorporationInventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
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Patent number: 7427881Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: GrantFiled: April 4, 2006Date of Patent: September 23, 2008Assignee: Altera CorporationInventors: Gregg Starr, Edward Aung
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Patent number: 7352766Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ?X/N? groups of cells; a read-write control block receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for the group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of the group of cells are stored in the N memory modules; the MCP address being the same as the group address.Type: GrantFiled: September 20, 2002Date of Patent: April 1, 2008Assignee: Alcatel LucentInventors: Kizito Gysbertus Antonius Van Asten, Faisal Dada, Edward Aung Kyi Maung
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Patent number: 7333570Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: GrantFiled: June 3, 2003Date of Patent: February 19, 2008Assignee: Altera CorporationInventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
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Publication number: 20080031385Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: ApplicationFiled: April 25, 2007Publication date: February 7, 2008Applicant: Altera CorporationInventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
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Patent number: 7227918Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: GrantFiled: March 13, 2001Date of Patent: June 5, 2007Assignee: Altera CorporationInventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
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Patent number: 7126959Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into [X/N] groups of cells; a read-write control block comprising a means for receiving cells from the write port and storing each cell, which belongs to the same group, in a selected different one of the N memory modules at the same memory address (the group address); a multi-cell pointer (MCP) storage for storing an MCP for said group of cells (an associated MCP) at an MCP address, the MCP having N memory module identifiers to record the order in which cells of said group of cells are stored in the N memory modules; and the MCP address being the same as the group address. Corresponding methods for storing cells and/or storing and retrieving variable size packet in such memory are also provided.Type: GrantFiled: July 15, 2002Date of Patent: October 24, 2006Assignee: Tropic Networks Inc.Inventors: Kizito Gysbertus Antonius Van Asten, Faisal Dada, Edward Aung Kyi Maung
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Publication number: 20060197558Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: ApplicationFiled: April 4, 2006Publication date: September 7, 2006Inventors: Greg Starr, Edward Aung
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Patent number: 7046048Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: GrantFiled: August 9, 2004Date of Patent: May 16, 2006Assignee: Altera CorporationInventors: Greg Starr, Edward Aung
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Patent number: 6981200Abstract: A method for transmission of digital data in a form of data packets through links carrying data packets with error correction, includes the steps of enveloping a sent packet data, first with an error detection scheme, and secondly with an error correction scheme. The error correction applies to both the sent packet data and to the error detection field. If an error in either of these fields occurs, the error correction scheme attempts to correct it. Error correction may fail in which case the packet is dropped. If error correction does not fail, there is still a possibility that there was an error which error correction did not correct correctly, or did not detect at all because the power of the correction scheme was exceeded. In these cases, the error detection scheme provides a method or means to detect such errors and drop the packet. Corresponding interconnect system with error correction, encode and decode for such are also provided.Type: GrantFiled: December 5, 2001Date of Patent: December 27, 2005Assignee: Tropic Networks Inc.Inventors: Edward Aung Kyi Maung, Bijan Raahemi, Thomas George Zboril, Kizito Gysbertus Antonius Van Asten
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Patent number: 6891401Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: GrantFiled: August 5, 2002Date of Patent: May 10, 2005Assignee: Altera CorporationInventors: Greg Starr, Edward Aung
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Publication number: 20050012525Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: ApplicationFiled: August 9, 2004Publication date: January 20, 2005Inventors: Greg Starr, Edward Aung
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Publication number: 20030212930Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: ApplicationFiled: June 3, 2003Publication date: November 13, 2003Applicant: Altera CorporationInventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee
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Publication number: 20030174699Abstract: A high-speed packet memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;Type: ApplicationFiled: July 15, 2002Publication date: September 18, 2003Inventors: Kizito Gysbertus Antonius Van Asten, Faisal Dada, Edward Aung Kyi Maung
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Publication number: 20030174708Abstract: A high-speed memory is provided, the memory having a write port and a read port and comprised of the following: a plurality of N memory modules for storing fixed size cells, which are segments of a variable size packet divided into X cells, the X cells being grouped into ┌X/N┐ groups of cells;Type: ApplicationFiled: September 20, 2002Publication date: September 18, 2003Inventors: Kizito Gysbertus Antonius Van Asten, Faisal Dada, Edward Aung Kyi Maung
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Publication number: 20030051204Abstract: A method for transmission of digital data in a form of data packets through links carrying data packets with error correction, includes the steps of enveloping a sent packet data, first with an error detection scheme, and secondly with an error correction scheme. The error correction applies to both the sent packet data and to the error detection field. If an error in either of these fields occurs, the error correction scheme attempts to correct it. Error correction may fail in which case the packet is dropped. If error correction does not fail, there is still a possibility that there was an error which error correction did not correct correctly, or did not detect at all because the power of the correction scheme was exceeded. In these cases, the error detection scheme provides a method or means to detect such errors and drop the packet. Corresponding interconnect system with error correction, encode and decode for such are also provided.Type: ApplicationFiled: December 5, 2001Publication date: March 13, 2003Inventors: Edward Aung Kyi Maung, Bijan Raahemi, Thomas George Zboril, Kizito Gysbertus Antonius Van Asten
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Publication number: 20030034820Abstract: In one aspect, an embodiment provides a clock loss sense and switchover circuit and method in which clock switchover is responsive to loss of a primary signal and to additional switch command signaling. In another aspect, an embodiment provides a clock loss sense circuit and method that utilizes counters and reset signals to compare a primary clock and secondary clock signal.Type: ApplicationFiled: August 5, 2002Publication date: February 20, 2003Inventors: Greg Starr, Edward Aung
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Patent number: 6469553Abstract: A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals.Type: GrantFiled: March 19, 2001Date of Patent: October 22, 2002Assignee: Altera CorporationInventors: Chiakang Sung, Robert R. N. Bielby, Richard G. Cliff, Edward Aung
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Publication number: 20010033188Abstract: A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). The circuitry may be part of a larger system.Type: ApplicationFiled: March 13, 2001Publication date: October 25, 2001Inventors: Edward Aung, Henry Lui, Paul Butler, John Turner, Rakesh Patel, Chong Lee