Abstract: A low signal margin detect circuit for detecting reduced signal levels in differential current switch (DCS) or current switch emitter follower (CSEF) circuits. The circuit is connected to the outputs of a DCS circuit or to the output of a current switch emitter follower circuit and a reference voltage. A signal difference between the inputs is determined and, if less than an established amount, an error signal is generated. The detect circuit is enabled by a TESTBIAS signal. Two error signals are developed, ERRORX and ERRORY, which can be dotted with the error signals from adjacent circuits in the X and Y directions. This enables detection of the failing circuit through the use of appropriate error signal detection devices.

Abstract: An output stage device for an enhanced differential current switch. The output stage receives a differential signal pair from a prior logic stage and must shift the output signals to the levels necessary for the next stage. The output stage has a differential pair of emitter followers that are capacitively cross coupled. Capacitors couple the collector of a first transistor to the emitter of the second. The capacitors can be formed from forward biased diodes or transistors. The result is a more rapid falling output transition while reducing power requirements.

Abstract: A compensating upshift circuit providing low signal degradation and operating at high speed and at low power. Capacitor shunted diodes cross-couple the collectors and bases of two transistors. The cross-coupling eliminates signal swing degradation in the upshift circuit and controls current through the two collector resistors. Equalized collector resistor current eliminates signal swing degradation while providing an upshift circuit with short delays. The capacitor shunted diodes can be replaced by diode connected transistors configured to provide the necessary collector-base capacitance.

Abstract: A low power push pull off chip driver for differential cascode current circuitry is described that includes the collectors of a differential pair directly coupled to bases of a push pull driver and level shifters coupled to the input of the differential pair to prevent saturation of the differential pair.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more of less binary ones or zeros.

Abstract: A masterslice cell wireable to form any of a selected book set of two level differential cascode current switch basic circuits. Twenty percent increased performance is provided as compared with ECL masterslice circuits running at the same power. In spite of increased wire due to differential logic, and potential increased complexity in design software, the invention is actually readily adaptable to existing masterslice design systems.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

Abstract: A method and apparatus for testing very large scale integrated circuit devices, most particularly Level Sensitive Scan Design (LSSD) devices, by applying differently configured sequences of pseudo-random patterns in parallel to each of the input terminals of the device under test, collecting the output responses from each of the output terminals in parallel, combining these outputs to obtain a signature which is a predetermined function of all of the sequences of parallel outputs and comparing the test signature with a known good signature obtained by computer simulation. The input test stimuli are further altered in a predetermined fashion as a function of the structure of the device to be tested, to individually weight the inputs in favor of more or less binary ones or zeros.

Abstract: A PLA is constructed to improve random testing. Section circuits are provided that permit disabling sections of the output lines that are called segments so that the circuit can be tested one segment at a time. Selection circuits are also provided for enabling the product term lines only one at a time. Thus, while random test signals are conventionally applied to the PLA input terminals for test, only a small portion of the PLA is enabled for the test. Control signals for the selection circuits are generated randomly so that the portion of the PLA that is tested is varied randomly.

Abstract: An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.