Patents by Inventor Edward B. Harris
Edward B. Harris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9897319Abstract: The present disclosure relates combustor configurations for a gas turbine engine. In one embodiment, a combustor includes a combustor shell enclosing a first area of free space, and an igniter for the combustor shell, the igniter including a distal end. The combustor also includes one or more elements configured to retain the igniter and to interface with the combustor shell, wherein the igniter is retained that the distal end of the igniter is recessed from the first area of free space. According to another embodiment, a combustor configuration may include one or more elements configured to retain an igniter and interface with the combustor shell, wherein the one or more elements define a boundary between the combustor shell and one or more elements, and wherein the igniter is retained within the one or more elements such that the distal end of the igniter is recessed from the boundary.Type: GrantFiled: February 25, 2015Date of Patent: February 20, 2018Assignee: UNITED TECHNOLOGIES CORPORATIONInventors: Robert M. Sonntag, Michael Youssef, Edward B. Harris, Richard A. Long
-
Publication number: 20160245517Abstract: The present disclosure relates combustor configurations for a gas turbine engine. In one embodiment, a combustor includes a combustor shell enclosing a first area of free space, and an igniter for the combustor shell, the igniter including a distal end. The combustor also includes one or more elements configured to retain the igniter and to interface with the combustor shell, wherein the igniter is retained that the distal end of the igniter is recessed from the first area of free space. According to another embodiment, a combustor configuration may include one or more elements configured to retain an igniter and interface with the combustor shell, wherein the one or more elements define a boundary between the combustor shell and one or more elements, and wherein the igniter is retained within the one or more elements such that the distal end of the igniter is recessed from the boundary.Type: ApplicationFiled: February 25, 2015Publication date: August 25, 2016Inventors: Robert M. SONNTAG, Michael YOUSSEF, Edward B. HARRIS, Richard A. LONG
-
Patent number: 8890338Abstract: A chip and a method of fabricating the chip for low cost chip identification circuitry. In one embodiment, a method of manufacturing an integrated circuit includes formation of a multi-level metallization structure including a pad level comprising programming pads. A plurality of active devices are formed on a substrate, and multiple levels of metallization are formed over the active devices, connecting some of the active devices to form programmable circuitry. The programmable circuitry is connected to pairs of programming pads on the bond pad level. Programming pads in some of the pairs are selectively connected to one another by using conductive ink deposited with maskless inkjet printing techniques. The pads are then covered with a non-conductive protective layer.Type: GrantFiled: September 27, 2006Date of Patent: November 18, 2014Assignee: Agere Systems, Inc.Inventor: Edward B. Harris
-
Patent number: 8624352Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.Type: GrantFiled: November 24, 2010Date of Patent: January 7, 2014Assignee: LSI CorporationInventors: Bonnie E. Weir, Edward B. Harris, Ramnath Venkatraman
-
Patent number: 8566377Abstract: A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.Type: GrantFiled: May 23, 2008Date of Patent: October 22, 2013Assignee: Agere Systems LLCInventors: Edward B. Harris, Richard Hogg, Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
-
Patent number: 8310275Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.Type: GrantFiled: March 27, 2008Date of Patent: November 13, 2012Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Che Choi Leung
-
Patent number: 8242603Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.Type: GrantFiled: December 10, 2007Date of Patent: August 14, 2012Assignee: Agere Systems Inc.Inventors: Joseph J. Check, Edward B. Harris, Lyle K. Mantz, II, Richard R. Kiser, Patricia J. Leith
-
Publication number: 20120126364Abstract: An IC capacitor bank includes a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces. A fusible trace located on an end of one of the pair of conductive traces forms a capacitor column connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column. Additionally, a method of manufacturing an IC capacitor bank includes providing a plurality of high-k metal-insulator-metal (MIM) capacitors connected to a pair of conductive traces and locating a fusible trace on an end of the pair of conductive traces to form a capacitor column that is connected between supply lines, such that failure of a dielectric in the MIM capacitors causes the fusible trace to at least partially open thereby limiting a fault current in the capacitor column.Type: ApplicationFiled: November 24, 2010Publication date: May 24, 2012Applicant: LSI CorporationInventors: Bonnie E. Weir, Edward B. Harris, Ramnath Venkatraman
-
Patent number: 8119501Abstract: Provided is a method for separating a semiconductor wafer into individual semiconductor dies. The method for separating the semiconductor wafer, among other steps, may include implanting an impurity into regions of a semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions. The method for separating the semiconductor wafer may further include separating the semiconductor wafer having the impurity into individual semiconductor dies along the weakened regions.Type: GrantFiled: November 16, 2009Date of Patent: February 21, 2012Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Kurt G. Steiner
-
Patent number: 8105912Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.Type: GrantFiled: May 31, 2011Date of Patent: January 31, 2012Assignee: Agere Systems Inc.Inventor: Edward B. Harris
-
Patent number: 8054668Abstract: In an illustrative embodiment, a memory cell comprises a first and a second MOSFET, wherein the first MOSFET undergoes a process to modify the threshold voltage such that a modified threshold voltage represents a first stored logic value. By determining which one of the first and the second MOSFETs has an altered threshold voltage, the stored logic value is determinable. The threshold voltage of the first MOSFET is altered by supplying current through a MOSFET gate, causing a gate heating effect that results in a threshold voltage shift.Type: GrantFiled: October 30, 2008Date of Patent: November 8, 2011Assignee: Agere Systems Inc.Inventor: Edward B. Harris
-
Patent number: 8039923Abstract: The specification describes matched capacitor pairs that employ interconnect metal in an interdigitated form, and are made with an area efficient configuration. In addition, structural variations between capacitors in the capacitor pair are minimized to provide optimum matching. According to the invention, the capacitor pairs are interdigitated in a manner that ensures that the plates of each pair occupy common area on the substrate. Structural anomalies due to process conditions are compensated in that a given anomaly affects both capacitors in the same way. Two of the capacitor plates, one in each pair, are formed of comb structures, with the fingers of the combs interdigitated. The other plates are formed using one or more plates interleaved between the interdigitated plates.Type: GrantFiled: November 10, 2009Date of Patent: October 18, 2011Assignee: Agere Systems Inc.Inventors: Edward B. Harris, Canzhong He, Che Choi Leung, Bruce W. McNeill
-
Patent number: 8037771Abstract: An electronic pressure-sensing device 100 comprising a transistor 105 located on a substrate 110. The device also comprises a linker arm 115 that has a tip 120 which is configured to touch a contact region 125 of the substrate that is near the transistor. The device also comprises a pressure converter 130 that is mechanically coupled to the linker arm. The pressure converter is configured to cause, in response to a pressure change, the tip to impart a force capable of changing an electrical conductivity of the transistor.Type: GrantFiled: May 13, 2009Date of Patent: October 18, 2011Assignee: LSI CorporationInventor: Edward B. Harris
-
Publication number: 20110230032Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.Type: ApplicationFiled: May 31, 2011Publication date: September 22, 2011Inventor: Edward B. Harris
-
Patent number: 7977721Abstract: A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.Type: GrantFiled: April 30, 2008Date of Patent: July 12, 2011Assignee: Agere Systems Inc.Inventor: Edward B. Harris
-
Publication number: 20110043249Abstract: An IO interface circuit for use in a high voltage tolerant application is provided. The IO interface circuit includes a signal pad and at least a first parasitic bipolar transistor having an emitter adapted for connection to a voltage return of the interface circuit, a base adapted to receive a first control signal, and a collector connected directly to the signal pad in an open collector configuration. The interface circuit further includes a MOS control circuit coupled to the parasitic bipolar transistor and being operative to generate the first control signal. The IO interface circuit may further include an active pull-up circuit connected between a voltage supply of the interface circuit and the signal pad.Type: ApplicationFiled: March 27, 2008Publication date: February 24, 2011Inventors: Edward B. Harris, Che Choi Leung
-
Publication number: 20110022648Abstract: A random number generator circuit includes a first memory having multiple storage elements. Each of the storage elements has an initial state corresponding thereto when powered up by a voltage supply source applied to the first memory. The first memory is operative to generate a first signal including multiple bits indicative of the respective initial states of the storage elements. The random number generator circuit further includes an error correction circuit coupled to the first memory. The error correction circuit is operative to receive the first signal and to correct at least one bit in the first signal that is not repeatable upon successive applications of power to the first memory to thereby generate a second signal. The second signal is a random number that is repeatable upon successive applications of power to the first memory.Type: ApplicationFiled: May 23, 2008Publication date: January 27, 2011Inventors: Edward B. Harris, Richard Hogg, Ross A. Kohler, Richard J. McPartland, Wayne E. Werner
-
Publication number: 20100288048Abstract: An electronic pressure-sensing device 100 comprising a transistor 105 located on a substrate 110. The device also comprises a linker arm 115 that has a tip 120 which is configured to touch a contact region 125 of the substrate that is near the transistor. The device also comprises a pressure converter 130 that is mechanically coupled to the linker arm. The pressure converter is configured to cause, in response to a pressure change, the tip to impart a force capable of changing an electrical conductivity of the transistor.Type: ApplicationFiled: May 13, 2009Publication date: November 18, 2010Applicant: LSI CorporationInventor: Edward B. Harris
-
Publication number: 20100270684Abstract: An integrated circuit (IC) structure includes a semiconductor substrate having a plurality of memory bits including IC identification information and a plurality of alternating metal and via layers thereabove. The IC structure includes a bond pad layer formed over a top one of the metal layers. The bond pad layer includes a plurality of pins connected to respective ones of the plurality of memory bits through the metal and via layers, at least one first pad connected to a higher voltage power supply rail and at least one second pad is connected to a lower voltage power supply rail. The bond pad layer has a plurality of circuit segments therein that each connects a respective one of the plurality of pins to either the at least one first pad or the at least one second pad for programming the IC identification information into the memory bit corresponding to that pin.Type: ApplicationFiled: December 10, 2007Publication date: October 28, 2010Applicant: AGERE SYSTEMS INC.Inventors: Joseph J. Check, Edward B. Harris, Lyle K. Mantz, II, Richard R. Kiser, Patricia J. Leith
-
Publication number: 20100221893Abstract: Provided is a method for separating a semiconductor wafer into individual semiconductor dies. The method for separating the semiconductor wafer, among other steps, may include implanting an impurity into regions of a semiconductor wafer proximate junctions where semiconductor dies join one another, the impurity configured to disrupt bonds in the semiconductor wafer proximate the junctions and lead to weakened regions. The method for separating the semiconductor wafer may further include separating the semiconductor wafer having the impurity into individual semiconductor dies along the weakened regions.Type: ApplicationFiled: November 16, 2009Publication date: September 2, 2010Applicant: AGERE SYSTEMS INC.Inventors: Edward B. Harris, Kurt G. Steiner