Abstract: A highly filled, extruded solid surface sheet composite which has improved heat resistance, solvent resistance, and mar resistance by combination of glassy polymer and semi-crystalline polymer.

Abstract: A computer network system for multiple processing elements in which the multiple processing elements are coupled to a single network bus such that computer instructions from the processing elements may be transimtted simultaneously over the same network during one time interval by more than one processing element. A memory stores the instructions and a controller accepts instructions from one of the processing elements but rejects instructions from all other elements and stores and queues the rejected instructions for subsequent acceptance.

Abstract: A local area network (LAN) communications bus arrangement comprises a multiprocessor (.mu.P) bus, a direct memory access bus, and an adapter bus. The microprocessor bus permits the attachment of various computer elements while providing other integrity and communication functions to other computer elements or computer systems beyond the bus. The communications bus arrangement includes an adapter interface having up to four daughterboards. Each daughterboard has odd and even numbered connectors. The daughterboards are designed to handle control, data and address lines on the connectors. These daughterboards are the hardware means by which communications with LANs which are attached to the bus arrangement are accomplished with processes, disks tapes, memories, attached to the proprietary bus.

Abstract: A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (.mu.P) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

Abstract: Data is transferred between a main memory in a data processing system and communication channels under the control of communications control blocks provided in an auxiliary memory, each of which control blocks includes a starting address, range and status information so as to enable the transfer of data to data blocks included in the main memory as indicated by the starting address in the control blocks. A predetermined number of control blocks is allocated in the auxiliary memory for each communications channel and the transfer of all such data is performed utilizing as many of the predetermined number of control blocks as required for the channel until the transfer is complete as indicated by the last such control block utilized in the transfer. Control blocks are loaded in the auxiliary memory under control of the central processor of the system and are periodically accessed by the processor to determine the status of data transfer operations.