Patents by Inventor Edward BIDDULPH

Edward BIDDULPH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • REDUCING FALSE POSITIVE RAY TRAVERSAL USING POINT DEGENERATE CULLING
    Publication number: 20250104333
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: December 6, 2024
    Publication date: March 27, 2025
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • Reducing false positive ray traversal using point degenerate culling
    Patent number: 12198252
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: January 14, 2025
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
  • Reducing false positive ray traversal in a bounding volume hierarchy
    Patent number: 12198251
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: January 14, 2025
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
  • Reducing false positive ray traversal using ray clipping
    Patent number: 12106423
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: October 1, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Gregory Muthler, John Burgess, Magnus Andersson, Ian Kwong, Edward Biddulph
  • REDUCING FALSE POSITIVE RAY TRAVERSAL IN A BOUNDING VOLUME HIERARCHY
    Publication number: 20240095993
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • REDUCING FALSE POSITIVE RAY TRAVERSAL USING POINT DEGENERATE CULLING
    Publication number: 20240095994
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • REDUCING FALSE POSITIVE RAY TRAVERSAL USING RAY CLIPPING
    Publication number: 20240095995
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: NVIDIA Corporation
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH