Abstract: Systems, methods, and apparatuses for autonomous functional testing of a processor are described.

Abstract: Examples include techniques for debug, survivability, and infield testing of a system-on-a-chip (SoC) or system-on-a-package (SoP) that can be configured as a processor. The techniques include using an agent coupled with a network-on-chip (NoC) fabric to launch transaction over the NoC fabric to test or debug agents, devices, or devices coupled to the SoC or SoP and/or interconnected to the NoC fabric.

Abstract: Systems, methods, and apparatuses for autonomous functional testing of a processor are described.

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

Abstract: A tristate and pass-gate based multiplexer circuit structure is described with full scan coverage capability. The circuit provides deterministic state at its output avoiding high impedance (Z) logic states in silicon. This is realized using a pull-up transistors, pull-down transistors, or through stages of combinational logic combining the multiplexer selects/enables feeding a pull-up or pull-down transistors.

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

Abstract: In some examples, multiple requesters request use of a resource and a single request is granted. A priority scheme can be set such that among pairs of requests, the lower numbered request is advanced. After one or more rounds of arbitration, a determination is made as to which request to grant. In a case where higher priority requesters are to be identified, masks can be used to mask out requests from non-higher priority requesters in a subsequent round. A mask can be generated for any requester that is at or below the priority level of the requester that had its request granted. Accordingly, when a high priority arbiter is used to set another priority level, the mask(s) can be used to indicate the higher priority requests.