Patents by Inventor Edward Brian Acheson

Edward Brian Acheson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for consolidating and applying manufacturing constraints
    Patent number: 11714948
    Abstract: The present disclosure relates to a system and method for use in an electronic circuit design. Embodiments may include receiving, using a processor, one or more DFM rules files from at least one PCB fabricator and importing the one or more DFM rules files to a DFM rule aggregator database. Embodiments may also include grouping one or more rules associated with the one or more DFM rules files using an automated or manual operation. Embodiments may further include performing automatic or manual rule aggregation on the grouped rules based upon, at least in part, rules aggregation information including a DFM template file.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: August 1, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Utpal Bhattacharyya, Randall Scott Lawson, Edward Brian Acheson, Amit Sharma