Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Abstract: A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Abstract: Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

Abstract: Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

Abstract: String matching is a ubiquitous problem that arises in a wide range of applications in computer science, e.g., packet routing, intrusion detection, web querying, and genome analysis. Due to its importance, dozens of algorithms and several data structures have been developed over the years. A recent breakthrough in this field is the FM-index, a data structure that synergistically combines the Burrows-Wheeler transform and the suffix array. In software, the FM-index allows searching (exact and approximate) in times comparable to the fastest known indices for large texts (suffix trees and suffix arrays), but has the additional advantage to be much more space-efficient than those indices. This disclosure discusses an FPGA-based hardware implementation of the FM-index for exact and approximate pattern matching.

Abstract: String matching is a ubiquitous problem that arises in a wide range of applications in computer science, e.g., packet routing, intrusion detection, web querying, and genome analysis. Due to its importance, dozens of algorithms and several data structures have been developed over the years. A recent breakthrough in this field is the FM-index, a data structure that synergistically combines the Burrows-Wheeler transform and the suffix array. In software, the FM-index allows searching (exact and approximate) in times comparable to the fastest known indices for large texts (suffix trees and suffix arrays), but has the additional advantage to be much more space-efficient than those indices. This disclosure discusses an FPGA-based hardware implementation of the FM-index for exact and approximate pattern matching.