Abstract: A switching fabric handles transactions using a protocol that directs packets based on path routing information. Components participate in transactions using a protocol that issues packets based on physical location of a destination device over the switching fabric, by establishing a virtual link partner relationship between the components.

Abstract: A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

Abstract: A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.

Abstract: The present invention provides a screw comprising a head and a threaded shank, wherein the shank is covered with a coating at least 60% of the length thereof from the end, the coating includes microcapsules that contain a viscous fluid with an appropriate level of viscosity. Shavings, including powdered shavings due to friction and exfoliations that may be generated during the screwing process, will be held, so that they will not fall, at the surface of the shank by the viscous fluid coming out of the microcapsules.

Abstract: High-speed optical interconnects are formed between I/O ports on an electromagnetic device and at least one optical communication channel via a vertical cavity surface emitting laser (VCSEL) array. The VCSEL array of the interconnect is separated into at least two segments, each segment comprising at least one optical communication channel coupled to a respective I/O port.

Abstract: A method of self-refresh in a memory array includes initializing a programmable refresh counter of a memory module to an offset value from at least another memory module in the memory array. A data line carrying a system-wide self-refresh indicator signal is interrogated to determine whether any memory module is in a self-refresh mode. The self-refresh mode for the memory module is entered if the programmable refresh counter indicates that a self-refresh cycle is due, and it is determined that no other memory modules are in the self-refresh mode.

Abstract: A multiple-domain processing system includes a multi-dimensional switching fabric to provide intra-domain and inter-domain communication within the system.

Abstract: Embodiments of a method and/or apparatus for a switch fabric in a data transport system are disclosed.

Abstract: In a gate array having a plurality of free transistors and target transistors, a method and apparatus for protecting a gate electrode of a target transistor from gate charge by employing a free transistor as a gate electrode protection device. A target transistor is a transistor that has been determined to need gate charging protection. A free transistor is a transistor in the gate array which is not used to implement the logic design as embodied in the gate array. Initially, a base array is formed without any metal layers. Then, a determination is made as to which transistors require gate charging protection. The gate electrode of each target transistor determined to require gate charging is coupled to an associated drain or source electrode of a free transistor of the gate array. The gate electrode of the free transistor is connected to an appropriate voltage reference to turn the free transistor off.

Abstract: The present invention discloses a system and method of testing semiconductor memory devices formed as integrated circuits on semiconductor substrates. The present invention allows parallel testing of arrays using only one input/output (I/O or DQ) to write to the arrays and only two DQs to read from the arrays. The broad search should be directed to methods of compressing the time and number of I/O's required for testing wide, high pin count, or highly partitioned memory arrays. The specific method of this invention comprises simultaneously writing the same test bit to each array, simultaneously reading a common address from each array and comparing the output of each array to report a fail if all outputs are not the same.

Abstract: In a gate array having a plurality of free transistors and target transistors, a method and apparatus for protecting a gate electrode of a target transistor from gate charge by employing a free transistor as a gate electrode protection device. A target transistor is a transistor that has been determined to need gate charging protection. A free transistor is a transistor in the gate array which is not used to implement the logic design as embodied in the gate array. Initially, a base array is formed without any metal layers. Then, a determination is made as to which transistors require gate charging protection. The gate electrode of each target transistor determined to require gate charging is coupled to an associated drain or source electrode of a free transistor of the gate array. The gate electrode of the free transistor is connected to an appropriate voltage reference to turn the free transistor off.

Abstract: A frame buffer construction and data storage technique for computer graphics display systems are presented employing a plurality of on-chip color registers. The plurality of on-chip color registers facilitate block writing and flash writing of multiple color information into the main frame buffer video memory. Addressing of the plurality of color registers is achieved at a column address strobe (CAS) cycle page mode rate for both the loading of the registers and the block or flash writing of the contents of the registers into the main memory array.

Abstract: An apparatus and method for enhancing serial access memory (SAM) performance incorporating a pipeline technique that removes a first bit clock cycle latency. In a video DRAM (VDRAM) read operation, accessed VDRAM data is provided simultaneously to the SAM and to a primary latch. The first bit of the VDRAM data is moved from the primary latch to a secondary output port of the memory apparatus ahead of the second through n.sup.th bits of the SAM data.

Abstract: The Benzofuranyl- and -thiophenyl-alkane-carboxylic acid derivatives are prepared Tby cyclisation of hydroxy acetophenones and related compounds or by Wittig-reaction of benzofuranyl aldehydes. The compounds can be used to prepared medicaments.