Abstract: Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.

Abstract: Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.