Abstract: The invention relates to an inter-chip communication protocol, based on a standard interface protocol, which is adapted to incorporate control, configuration and/or recovery information for computer chips, and the data encoded within communication packets of a communication layer above the physical layer of the interface protocol.

Abstract: Initialization of a bidirectional, self-timed parallel interface with capacitive coupling is provided. The self-timed interface includes master and slave nodes connected by a parallel bus comprising multiple AC differential wire pairs. The initialization includes automatically testing at least one wire pair of the multiple AC differential wire pairs for conductivity failure, wherein the testing is responsive to a link reset signal of a first frequency. The automatically testing includes employing a link test signal of a second frequency to test the at least one wire pair of the multiple AC differential wire pairs. The second frequency is a lower frequency than a third, operational signal frequency of the self-timed parallel interface, and the first frequency and the second frequency comprise different frequencies. An initialization testing and handshake approach between the master node and slave node is also provided.

Abstract: Initialization of a bidirectional, self-timed parallel interface with capacitive coupling is provided. The self-timed interface includes master and slave nodes connected by a parallel bus comprising multiple AC differential wire pairs. The initialization includes automatically testing at least one wire pair of the multiple AC differential wire pairs for conductivity failure, wherein the testing is responsive to a link reset signal of a first frequency. The automatically testing includes employing a link test signal of a second frequency to test the at least one wire pair of the multiple AC differential wire pairs. The second frequency is a lower frequency than a third, operational signal frequency of the self-timed parallel interface, and the first frequency and the second frequency comprise different frequencies. An initialization testing and handshake approach between the master node and slave node is also provided.

Abstract: The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations.