Patents by Inventor Edward Cho

Edward Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100735
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: September 24, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Patent number: 12027586
    Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Cho-eun Lee, Seok-hoon Kim, Sang-gil Lee, Edward Cho, Min-hee Choi, Seung-hun Lee
  • Publication number: 20230395661
    Abstract: An integrated circuit (IC) device including fin-type active regions parallel to each other on a substrate, the fin-type active regions extending in a first lateral direction, a first nanosheet stack apart from a fin top surface of a first fin-type active region selected from the fin-type active regions, the first nanosheet stack including at least one nanosheet facing the fin top surface of the first fin-type active region, a gate structure surrounding the first nanosheet stack, the gate structure extending in a second lateral direction, a first source/drain region in contact with one sidewall of the first nanosheet stack, and a second source/drain region in contact with another sidewall of the first nanosheet stack , wherein a greatest width of the first source/drain region is less than a greatest width of the second source/drain region in the second lateral direction may be provided.
    Type: Application
    Filed: January 4, 2023
    Publication date: December 7, 2023
    Applicant: Samsung Electronics Co., Ltd. Suwon-si
    Inventors: Sumin YU, Jungtaek KIM, Moonseung YANG, Seojin JEONG, Edward CHO, Seokhoon KIM, Pankwi PARK
  • Publication number: 20230352532
    Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.
    Type: Application
    Filed: July 5, 2023
    Publication date: November 2, 2023
    Inventors: Cho-eun LEE, Seok-hoon KIM, Sang-gil LEE, Edward CHO, Min-hee CHOI, Seung-hun LEE
  • Publication number: 20230207628
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Application
    Filed: March 1, 2023
    Publication date: June 29, 2023
    Inventors: Namkyu Edward CHO, Seung Soo HONG, Geum Jung SEONG, Seung Hun LEE, Jeong Yun LEE
  • Patent number: 11600698
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Patent number: 11508751
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: November 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Il Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
  • Publication number: 20210159246
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 27, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung Il KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
  • Publication number: 20210098577
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Patent number: 10930668
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Ii Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
  • Patent number: 10896957
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Publication number: 20200027895
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: February 11, 2019
    Publication date: January 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung II KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
  • Publication number: 20190288065
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Application
    Filed: May 30, 2018
    Publication date: September 19, 2019
    Inventors: Namkyu Edward CHO, Seung Soo HONG, Geum Jung SEONG, Seung Hun LEE, Jeong Yun LEE
  • Publication number: 20070240999
    Abstract: A bottle which allows for an additive to be held in a container within the receptacle of the bottle separately from the contents held in the receptacle of the bottle until the time for mixture desired by the user. The bottle having a receptacle and a mouth leading into the receptacle. The bottle having the container in the receptacle. The container being formed to hold a substance therein and release the substance into the receptacle when the container is pressed with at least a predetermined amount of pressure. The container having a first member and a second member overlapping at least a portion of the first member in a slideable engagement to define a cavity therein. The second member having an opening formed through the surface, which is sufficiently sized to allow for a discharge of a substance contained in the cavity to be discharged therethrough. A cover is formed on the second member closing the opening.
    Type: Application
    Filed: June 15, 2007
    Publication date: October 18, 2007
    Inventors: Edward Cho, Jeong-Oog Park
  • Publication number: 20070138033
    Abstract: A bottle which allows for an additive to be held in a container within the receptacle of the bottle separately from the contents held in the receptacle of the bottle until the time for mixture desired by the user. The bottle having a receptacle and a mouth leading into the receptacle. The bottle having the container in the receptacle. The container being formed to hold a substance therein and release the substance into the receptacle when the container is squeezed with at least a predetermined amount of pressure. The container having a first member and a second member overlapping at least a portion of the first member in a slideable engagement to define a cavity therein. The second member having an opening formed through the surface, which is sufficiently sized to allow for a discharge of a substance contained in the cavity to be discharged therethrough. A cover is formed on the second member closing the opening.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 21, 2007
    Inventor: Edward Cho
  • Patent number: 4450264
    Abstract: There are prepared acrylates and methacrylates of the formula ##STR1## wherein R is hydrogen or methyl, y is 1 to 3, z is 0 to 2, y+z is 3, and wherein A is the unit (I) ##STR2## wherein x is 0 to 4, or the unit (II) ##STR3## with the proviso that when A is unit II, then z is zero. The novel siloxane compounds can be copolymerized with (1) a monoethylenically unsaturated monomer having a polymerizable carbon-to-carbon double bond, and (2) a cross-linking agent having at least two polymerizable, ethylenically unsaturated bonds. The resulting copolymers have high oxygen permeability and proper hydrophilic property. They can be made substantially water non-absorptive. Contact lenses fabricated from such copolymers can, if desired, be worn continuously for long periods of time.
    Type: Grant
    Filed: August 9, 1982
    Date of Patent: May 22, 1984
    Assignee: Polymatic Investment Corp., N.V.
    Inventor: Edward Cho