Abstract: Execution of a processing task within a data processing system is controlled by executing the processing task including allocating memory areas for data storage and then suspending an actual execution path of said processing task at a given execution point to perform memory management. The memory management involves identifying one or more data items occurring in the course of execution and accessible to the processing task at the given execution point, which specify reference values pointing to respective ones for the memory areas. A correlation is determined between reference values corresponding to identified data items and memory areas allocated during the execution up to the given execution point. A memory management operation is performed on allocated memory areas in dependence upon results of the correlation.

Abstract: A data processing apparatus 2 is provided which supports two instruction sets. These two instruction sets share a common subset of instructions including at least one class of instructions, such as all of the coprocessor instructions. The common subset of instructions have the same instruction encoding once any differences due to storage order within memory have been compensated for e.g. endianness.

Abstract: Unhandled operation of a program instruction of a first instruction set, such as a Java bytecode, is detected. Instead of invoking a mechanism for directly dealing with that unhandled operation, one or more instructions from a second instruction set, such as ARM instructions, are instead used to emulate the instruction that was subject to the unhandled operation. If these instructions of the second instruction set are also subject to unhandled operation, then the mechanisms for dealing with unhandled operation within that second instruction set may be invoked to repair that operation. This approach is well suited to dealing with unhandled operation of variable length instructions being interpreted with a processor core having a native fixed length instruction set. In particular, prefetch aborts and unhandled floating point operations may be conveniently dealt with in this way.

Abstract: A data processing system 118 is provided that supports execution of both native instructions using a processor core and non-native instructions that are interpreted using either a hardware translator 122 or a software interpreter. Separate explicit return to non-native instructions and return to native instructions are provided for terminating subroutines whereby intercalling between native and non-native code may be achieved with reduced processing overhead. Veneer non-native subroutines may be used between native code and non-native main subroutines. The veneer non-native subroutines may be dynamically created within the stack memory region of the native mode system.

Abstract: A data processing system having a Harvard type architecture including a separate data store 8 and instruction store 6 is provided with an instruction interpreter 22 that dynamically modifies slow form instructions to fast form instructions. When a slow form instruction is encountered, the instruction interpreter makes a check within the data store whether a fast form of that instruction has already been provided. If a fast form of the instruction is present within the data store, then this is used instead of the slow form.

Abstract: A processing system has a processor core executing instructions of a first instruction set and an instruction translator for generating translator output signals corresponding to one or more instructions of the first instruction set so as to emulate instructions of a second instruction set. The instruction translator provides translator output signals specifying operations that are arranged so that the input variables to an instruction of the second instruction set are not changed until the final operation emulating that instruction is executed. An interrupt handler services an interrupt after execution of an operation of the instructions of the first instruction set.

Abstract: A data processing apparatus includes a processor core having a bank of registers. The bank of registers include a set of registers that are used for the storage of stack operands. Instructions from a second instruction set specifying stack operands are translated by an instruction translator into instructions of a first instruction set (or control signals corresponding to those instructions) specifying register operands. These translated instructions are then executed by the processor core. The instruction translator has multiple mapping states for controlling which registers corresponding to which stack operands within the stack. Changes between mapping states are carried out in dependence of stack operands being added to or removed from the set of registers.

Abstract: A data processing system supports execution of both native instructions and Java bytecodes using a hardware executer for the Java bytecodes where possible and a software instruction interpreter for the Java bytecodes where these are not supported by the hardware. The sequences of native instructions 26 within the software instruction interpreter that perform the processing for the Java bytecodes being interpreted terminate within a sequence terminating instruction BXJ that acts differently depending upon whether or not an enabled hardware executer 6 is detected to be present. If an enabled hardware executer is detected as present, then the execution of the next Java bytecode is attempted with this. If an active hardware executer is not present, then the next Java bytecode is passed directly to the software instruction interpreter.

Abstract: An interpreter invocation mechanism for switching between execution of native instruction words to interpreted instruction words uses a subroutine call instruction to start execution of the interpreter. The return address of the subroutine call instruction is used as an address pointer to the start of the interpreted code. The interpreted code may terminate with an Exit instruction whereupon normal native code execution resumes using the instruction at the immediately following memory address or alternatively with a Return instruction that recovers a return address previously stored to stack memory.

Abstract: The present invention provides a data processing apparatus and method for saving return state. The data processing apparatus comprises a processing unit for executing data processing instructions, the processing unit having a plurality of modes of operation, with each mode of operation having a corresponding stack for storing data associated with that mode. The processing unit is responsive to a return state data processing instruction to write return state data of the processing unit from its current mode of operation to a stack corresponding to a different mode of operation to the current mode of operation. This approach significantly reduces code size and improves interrupt latency over known prior art techniques.

Abstract: A data processing apparatus 2 is provided which supports two instruction sets. These two instruction sets share a common subset of instructions including at least one class of instructions, such as all of the coprocessor instructions. The common subset of instructions have the same instruction encoding once any differences due to storage order within memory have been compensated for e.g. endianness.

Abstract: Execution of a processing task within a data processing system is controlled by executing the processing task including allocating memory areas for data storage and then suspending an actual execution path of said processing task at a given execution point to perform memory management. The memory management involves identifying one or more data items occurring in the course of execution and accessible to the processing task at the given execution point, which specify reference values pointing to respective ones of the memory areas. A correlation is determined between reference values corresponding to identified data items and memory areas allocated during the execution up to the given execution point. A memory management operation is performed on allocated memory areas in dependence upon results of the correlation.

Abstract: A data processing system supports execution of both native instructions and Java bytecodes using a hardware executer for the Java bytecodes where possible and a software instruction interpreter for the Java bytecodes where these are not supported by the hardware. The sequences of native instructions 26 within the software instruction interpreter that perform the processing for the Java bytecodes being interpreted terminate within a sequence terminating instruction BXJ that acts differently depending upon whether or not an enabled hardware executer 6 is detected to be present. If an enabled hardware executer is detected as present, then the execution of the next Java bytecode is attempted with this. If an active hardware executer is not present, then the next Java bytecode is passed directly to the software instruction interpreter.

Abstract: Unhandled operation of a program instruction of a first instruction set, such as a Java bytecode, is detected. Instead of invoking a mechanism for directly dealing with that unhandled operation, one or more instructions from a second instruction set, such as ARM instructions, are instead used to emulate the instruction that was subject to the unhandled operation. If these instructions of the second instruction set are also subject to unhandled operation, then the mechanisms for dealing with unhandled operation within that second instruction set may be invoked to repair that operation. This approach is well suited to dealing with unhandled operation of variable length instructions being interpreted with a processor core having a native fixed length instruction set. In particular, prefetch aborts and unhandled floating point operations may be conveniently dealt with in this way.

Abstract: A data processing system 118 is provided that supports execution of both native instructions using a processor core and non-native instructions that are interpreted using either a hardware translator 122 or a software interpreter. Separate explicit return to non-native instructions and return to native instructions are provided for terminating subroutines whereby intercalling between native and non-native code may be achieved with reduced processing overhead. Veneer non-native subroutines may be used between native code and non-native main subroutines. The veneer non-native subroutines may be dynamically created within the stack memory region of the native mode system.

Abstract: A data processing system having a Harvard type architecture including a separate data store 8 and instruction store 6 is provided with an instruction interpreter 22 that dynamically modifies slow form instructions to fast form instructions. When a slow form instruction is encountered, the instruction interpreter makes a check within the data store whether a fast form of that instruction has already been provided. If a fast form of the instruction is present within the data store, then this is used instead of the slow form.

Abstract: The present invention provides a data processing apparatus and method for saving return state. The data processing apparatus comprises a processing unit for executing data processing instructions, the processing unit having a plurality of modes of operation, with each mode of operation having a corresponding stack for storing data associated with that mode. The processing unit is responsive to a return state data processing instruction to write return state data of the processing unit from its current mode of operation to a stack corresponding to a different mode of operation to the current mode of operation. This approach significantly reduces code size and improves interrupt latency over known prior art techniques.

Abstract: A processing system has an instruction pipeline (30) and a processor core. An instruction translator (42) for translating non-native instructions into native instruction operations is provided within the instruction pipeline downstream of the fetch stage (32). The instruction translator is able to generate multiple step sequences of native instruction operations in a manner that allows variable length native instruction operations sequences to be generated to emulate non-native instructions. The fetch stage is provided with a word buffer (62) that stores both a current instruction word and a next instruction word. Accordingly, variable length non-native instructions that span between instruction words read from the memory may be provided for immediate decode and multiple power consuming memory fetch avoided.

Abstract: A processing system provides both hardware instruction translation (68) and software instruction interpretation (84) mechanisms for supporting high level program instructions. All of the program instructions are supplied to the hardware translation unit (68) which forwards those instructions it does not itself support to the software interpretation mechanism (84). By routing all program instructions through the hardware translation unit (68), the hardware translation unit (86) is able to monitor when it is appropriate and safe to trigger a scheduling operation for controlling multitasking or multithreaded operations. The scheduling operations may be triggered based upon a count of executed program instructions or by using a timer based scheduling approach with the timer signal being qualified by a signal indicating an appropriate point within the cycle of execution of program instructions.

Abstract: Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.