Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.

Abstract: Examples described herein provide an apparatus having a circuit with a grounding circuit and a switch. The apparatus generally includes a gate induced drain leakage (GIDL) protection circuit coupled to the switch and to an output voltage. The GIDL protection circuit may include a switch protection circuit configured to maintain a drain voltage of the switch less than a first supply voltage (Vdd) when the circuit is in an OFF state; and a ground protection circuit configured to maintain a drain voltage of the grounding circuit less than the first supply voltage when the circuit is in an ON state.

Abstract: A temperature sensor includes a current source to produce a first bias current and a second bias current, a plurality of diodes, and temperature estimation circuitry. The plurality of diodes includes at least a first diode to receive the first bias current and a second diode to receive the second bias current. The temperature estimate circuitry measures a first voltage bias across the first diode resulting from the first bias current and a second voltage bias across the second diode resulting from the second bias current, and estimates a temperature of an environment of the temperature sensor based at least in part on the first voltage bias and the second voltage bias. The temperature sensor further includes error detection circuitry to measure at least one of the first or second bias currents and determine an amount of error in the temperature estimate based at least in part on the measurement.

Abstract: Examples described herein provide for a relaxation oscillator and corresponding methods of operation. In an example, a circuit includes a dynamically controllable current source, a capacitor, and an oscillator generation circuit. The dynamically controllable current source includes a digitally tunable current mirror configured to generate a current. The digitally tunable current mirror includes multiple transistors configured to be selectively electrically connected in parallel to alter a gain of the digitally tunable current mirror to control the current. The capacitor is selectively electrically connected to the dynamically controllable current source. The oscillator generation circuit is electrically connected to the capacitor. The oscillator generation circuit is configured to generate an oscillation signal in response to a voltage of the capacitor.

Abstract: A control circuit used in an integrated circuit device is described. The control circuit comprises a startup timer configured to generate a startup timing signal; a startup circuit configured to generate a startup control signal; and a switching element coupled between the startup circuit and a load; wherein the switching element applies the startup control signal to the load during a startup period associated with the startup timing signal. A method of controlling an operation of an integrated circuit device is also described.

Abstract: A voltage divider is described. The voltage divider comprises a pair of input nodes for receiving an input signal; a pair of output nodes configured to generate an output signal; a first capacitor having a first terminal coupled to a first output node of the pair of output nodes and a second terminal coupled to a second output node of the pair of output nodes; and a second capacitor having first terminal and a second terminal; a bypass switch having a first terminal coupled to the first terminal of the second capacitor and a second terminal coupled to the second terminal of the second capacitor; and a charge sharing switch coupled to the second terminal of the second capacitor; wherein the bypass switch and the charge sharing switch enable the sharing of charge between the first capacitor and the second capacitor.

Abstract: A circuit for extending the bandwidth of a termination block is described. The circuit comprises an I/O contact configured to receive an input signal; and a termination circuit coupled to the I/O contact, wherein the termination circuit comprises a plurality of trim legs coupled between a power supply and the I/O contact, each trim leg having a switch to control the impedance in the trim leg.

Abstract: Examples of the present disclosure provide out-of-range voltage detection and protection in integrated circuits (ICs). In some examples, an IC includes an envelope detector, a comparator, and a switch. The envelope detector is configured to generate an envelope signal of a signal and output the envelope signal on an output node of the envelope detector. A first input node of the comparator is coupled to the output node of the envelope detector. The comparator is configured to compare respective signals provided on the first and second input nodes of the comparator and generate a comparison signal in response to the comparison. The comparator is further configured to output the comparison signal on the output node of the comparator. The switch is connected between a protected node and a protection node and is configured to be selectively opened or closed based, at least in part, on the comparison signal.

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl

Abstract: An example voltage reference circuit includes: a reference circuit comprising a first circuit configured to generate a proportional-to-temperature current and corresponding first control voltage and a second circuit configured to generate a complementary-to-temperature current and corresponding second control voltage; a first current source coupled to a first load circuit, the first current source generating a sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the first load circuit generating a zero temperature coefficient (Tempco) voltage from the sum current; and a second current source coupled to a second load circuit, the second current source generating the sum current of the proportional-to-temperature current and the complementary-to-temperature current in response to the first and second control voltages, the second load circuit generating a negative Tempco voltage from the sum current and the compl

Abstract: An example method of trimming a voltage reference in an integrated circuit (IC) includes at a first temperature, sequencing through a first plurality of trim codes for a reference circuit of the voltage reference configured to generate a proportional-to-temperature current and a corresponding first control voltage, and a complementary-to-temperature current and a corresponding second control voltage. The method further includes measuring a voltage output of the voltage reference for each of the first plurality of trim codes to obtain first voltage output values. The method further includes at a second temperature, sequencing through a second plurality of trim codes for the reference circuit. The method further includes measuring the voltage output of the voltage reference for each of the second plurality of trim codes to obtain second voltage output values. The method further includes selecting a trim code for the reference circuit based on the first voltage output values and the second voltage output values.

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

Abstract: A circuit for receiving an input signal is described. The receiver comprises a first receiver input configured to receive a first input of a differential input signal; a second receiver input configured to receive a second input of a differential input signal; a differential pair having an inverting input and a non-inverting input; a first impedance matching element coupled to the differential pair, wherein the first impedance matching element provides DC impedance matching from the inverting input and non-inverting input of the differential pair; and a second impedance matching element coupled to the differential pair, wherein the second impedance matching element provides AC impedance matching from the inverting input and non-inverting input of the differential pair.

Abstract: Various example implementations are directed to circuits and methods for generating a clock signal. According to an example embodiment, a circuit arrangement includes a relaxation oscillator configured to output a clock signal. The clock signal has an oscillation frequency dependent on a reference current provided to the relaxation oscillator, an operating temperature of the relaxation oscillator, and a supply voltage used to power the relaxation oscillator. The circuit arrangement also includes a current source coupled to the relaxation oscillator and configured to generate the reference current. The current source is configured to adjust the reference current, in response to a change in one or more of the temperature of the relaxation oscillator and the supply voltage, to inhibit change in the oscillation frequency of the clock signal.

Abstract: In one example, a current steering circuit includes an output transistor pair responsive to a first gate bias voltage. The current steering circuit further includes a first switch comprising a first source-coupled transistor pair coupled to the output transistor pair and responsive to a first differential gate voltage, and a second switch comprising a second source-coupled transistor pair coupled to the output transistor pair and responsive to a second differential gate voltage. The current steering circuit further includes a current source configured to source a bias current. The current steering circuit further includes a third switch comprising a third source-coupled transistor pair coupled between the current source and each of the first switch and the second switch, the third source-coupled transistor pair responsive to a third differential gate voltage.

Abstract: In an example, a temperature-corrected voltage reference circuit for use in an integrated circuit (IC) includes a voltage reference circuit, a programmable gain amplifier, and a digital control circuit. The programmable gain amplifier includes a first input coupled to the voltage reference circuit, a second input coupled to receive a control signal, and an output coupled to provide a temperature-corrected voltage reference. The digital control circuit includes an input coupled to receive a temperature signal indicative of temperature of the IC and an output coupled to the second input of the programmable gain amplifier, the digital control circuit generating the control signal in response to the temperature signal.

Abstract: A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise.

Abstract: An embodiment of an apparatus is disclosed. For this embodiment of the apparatus, an interposer has first vias. First interconnects and second interconnects respectively are coupled on opposite surfaces of the interposer. A first portion of the first interconnects and a second portion of the first interconnects are spaced apart from one another defining an isolation region between them. A substrate has second vias. Third interconnects and the second interconnects are respectively coupled on opposite surfaces of the package substrate. A first portion of the first vias and a first portion of the second vias are both in the isolation region and are coupled to one another with a first portion of the second interconnects.

Abstract: A system for calibrating impedance of an input/output (I/O) buffer on a semiconductor die includes: the I/O buffer; a temperature sensor on the semiconductor die; and a supply sensor on the semiconductor die. The temperature sensor is configured to acquire temperature information for calibrating the I/O buffer. The supply sensor is configured to acquire voltage information for calibrating the I/O buffer. The I/O buffer comprises: a memory component coupled to the temperature and supply sensors and configured to store the acquired temperature or voltage information; a logic component coupled to the memory component; and a driver with driver legs. The driver is coupled to the logic component. The logic component is configured to generate driver control signals representing an on/off configuration for the driver legs of the driver based at least in part on the acquired temperature information or the acquired voltage information stored in the memory component.

Abstract: An apparatus for calibration of a signal converter is disclosed. This apparatus includes a first digital-to-analog converter (“DAC”) and a calibration system coupled to an output port of the first DAC. The calibration system includes a second DAC. The calibration system is configured to provide an adjustment signal responsive to a spurious spectral performance parameter in an output of the first DAC. The spurious spectral performance parameter is sensitive to a timing error associated with the first DAC. The calibration system is coupled to provide the adjustment signal to the first DAC to correct the timing error of the first DAC.