Abstract: A chip carrier has a cavity portion for receiving a semiconductor chip and a flange portion along at least a portion of a top perimeter of the cavity portion. The module preferably includes a substrate (e.g., a PCB or chip carrier substrate) having a slot for receiving the cavity portion of the chip carrier, with the flange portion of the chip carrier being supported by the substrate. The flange portion is preferably electrically conductive and grounded, so that appropriate conductive pads on the chip can be wire bonded to the flange, while other on-chip pads can be wire bonded to designated pads on the substrate surface.. The cavity portion is also preferably thermally conductive to provide a thermal path for the semiconductor chip. In another embodiment, a relatively thick flanged chip mounting pad is also received within a substrate slot to provide improved heat dissipation.

Abstract: A method of obtaining a distribution profile of electrically active ions, of one type conductivity, implanted into a semiconductor, of an opposite type conductivity, is carried out with the aid of an integral target of the semiconductor. The integral target is formed with a plurality of doped regions of different background impurity concentrations, respectively, therein. Each of the operations of annealing, angle-lapping, and staining the doped regions to determine P-N junction depths therein is carried out on all of the doped regions simultaneously. An enlarged photograph of the stained angle-lapped portions of the doped regions provides directly a histogram of the distribution profile.

Abstract: A planar bipolar transistor is made by the successive ion implantations of selected atoms into selected regions of a layer of doped single-crystal silicon on an insulating substrate, such as sapphire or spinel. The silicon layer is epitaxially grown, has a thickness of between 0.5 and 5 .mu.m, and is formed in two strata of different resistivities. A collector contact well is ion implanted into the upper stratum and annealed to diffuse it into the lower stratum of lower resistivity. The transistor is isolated, as a mesa, on the substrate; and an edge-guard region is ion implanted through the periphery of the mesa, except in the region of the emitter-base junction.

Abstract: A planar bipolar transistor is made by the successive ion implantations of selected atoms into selected regions of a layer of doped single-crystal silicon on an insulating substrate, such as sapphire or spinel. The silicon layer is epitaxially grown, has a thickness of between 0.5 and 5 .mu.m, and is formed in two strata of different resistivities. A collector contact well is ion implanted into the upper stratum and annealed to diffuse it into the lower stratum of lower resistivity. The transistor is isolated, as a mesa, on the substrate; and an edge-guard region is ion implanted through the periphery of the mesa, except in the region of the emitter-base junction.

Abstract: In one embodiment, a semiconductor device, such as an insulated-gate-field-effect-transistor (IGFET), is simultaneously radiation hardened with Al ions and its threshold voltage stabilized with halide ions, such as Cl ions, by bombarding a silicon dioxide gate insulator of the device with molecular ions of an aluminum halide, such as AlCl.sub.2 .sup.+ ions. In another embodiment, a surface (target) of silicon is bombarded with molecular AlCl.sub.2 .sup.+ ions to ion implant separate Al ions and Cl ions. There, an oxide layer subsequently thermally grown on the bombarded surface includes the Al ions and the Cl ions, and the oxide layer is radiation hardened and gettered.