Abstract: Disclosed is an apparatus for generating mask data suitable to produce a support pillar mask used in air dielectric interconnect structures. The apparatus includes a mask data scanner configured to select features having an interconnect dimension from a first mask. The features having the interconnect dimension being defined to electrically interconnect devices distributed on a substrate. The apparatus further includes a mask data comparing engine for comparing mask data associated with an intermediate support pattern and mask data associated with the features having the interconnect dimension selected by the mask data scanner. The comparing being configured to identify a mask area where the intermediate support pattern and the features having the interconnect dimension overlap. Preferably, the identified mask area defines the location of a plurality of pillars.

Abstract: A heat sink is formed on a bonded semiconductor on insulator (SOI) wafer. A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer. The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer. A conductive pillar is formed in the trench. The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer. In the preferred embodiment, the conductive pillar is formed of doped polysilicon. The doped polysilicon is of a conductivity type which is different than the conductivity type of the base. Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base.

Abstract: Disclosed is a method for automating support pillar design in air dielectric interconnect structures. The method includes selecting features having an interconnect dimension from a first mask. Providing an intermediate support pattern defining a pillar spacing. Identifying overlap regions where the features selected from the first mask overlap the intermediate support pattern. The method further including filtering the overlap regions to eliminate features that are less than the interconnect dimension. The filtering being configured to define discrete pillar locations associated with the first mask.

Abstract: A heat sink is formed on a bonded semiconductor on insulator (SOI) wafer. A trench is formed which extends from a top of the bonded SOI wafer through an isolation region of the bonded SOI wafer to a base of the bonded SOI wafer. The base of the bonded SOI wafer is located below the isolation region of the bonded SOI wafer. A conductive pillar is formed in the trench. The conductive pillar extends from the top of the bonded SOI wafer through the isolation region of the bonded SOI wafer and is physically in contact with but electrically insulated from the base of the bonded SOI wafer. In the preferred embodiment, the conductive pillar is formed of doped polysilicon. The doped polysilicon is of a conductivity type which is different than the conductivity type of the base. Out-diffusion from the doped polysilicon forms a region within the base which electrically insulates the conductive pillar from the base.

Abstract: A system and method for reducing the contact resistance associated with tungsten plug contacts to P-doped diffusion regions of a semiconductor device. Before or during the formation of the tungsten plug contacts, a high energy, low dosage of an N-dopant or neutral species such as silicon or germanium is implanted into the P-doped diffusion regions of the semiconductor device. The implantation causes lattice damage within the P-doped diffusion regions, enhancing diffusion of the P-dopant within the P-doped diffusion regions. This results in the P-dopant diffusing toward the contact, replacing dopant lost to segregation into the contact metalization, and thus reducing the contact resistance.

Abstract: The planarity of the dielectric layer over a processing layer is increased by adjustments made to a mask generated for patterning the processing layer. Active circuitry lines are generated for the mask. Also, a fill pattern is generated for the mask. The fill pattern is placed in areas of the mask not filled by the active circuitry lines. The active circuitry lines are combined with the fill pattern to produce a final pattern for the mask. In one embodiment, the fill pattern is generated by first over-sizing the active circuitry lines to form a first pattern. The first pattern is inverted to produce a negative of the first pattern. The negative of the first pattern serves as a marker layer. In addition, a dummy fill pattern is generated. An intersection of the marker layer and the dummy fill pattern is performed to produce an unsized fill pattern.

Abstract: A transistor is formed which has improved hot carrier immunity. On a substrate, between two source/drain regions, a gate region is formed over a dielectric region. An implant is used to dope the source/drain regions. After doping the source/drain regions, a tilted angle nitrogen implant is performed to implant nitrogen into areas of the dielectric region overlaying the drain/source regions of the transistor. The tilted angle nitrogen implant may be performed before or after forming spacer regions on sides of the gate region.

Abstract: A self-aligned MOSFET incorporating a punchthrough implant, and the method for forming such a transistor. A dielectric layer is used as a hard mask over a semiconductor substrate. A portion of the dielectric layer is removed to expose a region of the semiconductor substrate. A punchthrough implant is made with the remaining portion of the dielectric layer acting as a mask layer such that the doping concentration is raised by the punchthrough implant only in the exposed region of the semiconductor substrate. A doped layer of polysilicon is formed over the region into which the implant was made to provide a self-aligned gate over the highly doped region. A source and drain are formed on opposite sides of the doped region. A protective layer is formed over the device and metallized contacts are formed to the source, drain, and gate.

Abstract: A resistor is connected to the source/drain of a transistor and used as a load element of a memory cell. A trench is formed which extends from a top of the wafer through an isolation region of the wafer to a silicon base of the wafer. The silicon base of the wafer is located below the isolation region of the wafer. A resistive layer of material is formed in the trench. The resistive layer extends from the top of the wafer through the isolation region of the wafer and is electrically connected to the silicon base of the wafer. The resistor is connected to other circuitry on the wafer, for example, by implanting into the wafer atoms of a first conductivity type into a region immediately adjacent to the resistive layer of material in the trench. In the preferred embodiment, the resistive layer of material is deposited polysilicon.

Abstract: A memory cell includes gated diodes as load elements. For example, the memory cell includes a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor, a fourth transistor, a first gated diode and a second gated diode. The first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line. The second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line. The third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor. The fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor.

Abstract: A bipolar transistor is fabricated in a CMOS-compatible process with a laterally graded emitter structure that is fabricated in a "top-down" implant process. The laterally graded emitter decreases electric field intensities in the emitter-base junction under reverse bias, thus reducing hot carrier generation and improving emitter-base junction breakdown voltage. High current gain is further maintained by establishing sharply defined emitter-base junctions. During fabrication a blocking layer and overlying cap layer are formed in an inverted "T" shape over a desired emitter window region. Lateral projection of the cap ledges are used to define the laterally graded emitter width, while the distance separating the cap ledges defines the width of the central emitter region. The central emitter region is implanted and driven-in to a desired depth, after which the protective cap is removed.

Abstract: For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer.