Abstract: A multilayer substrate provides predetermined connections to and between a plurality of integrated circuit chips mounted thereon. A plurality of layers mounted on a surface of a substrate has a plurality of layers comprising a plurality of dielectric layers, a first plurality of metallic layers, and a second plurality of metallic layers. The first plurality of metallic layers has a predetermined pattern for forming the predetermined connections, these being the x-lines and y-lines. Each of the second plurality of metallic layers provides a predetermined voltage level to the integrated circuit chips, and each of the second metallic layers has a screen-like structure. Each of the first and second metallic layers is insulated from the other metallic layers by one of the dielectric layers, except for desired interconnections between the x-lines y-lines, and power layer (or power plane).