Abstract: In order to reduce the time it takes on-chip circuitry to generate an internal enabling signal from an external clock signal and an external enabling signal, the external clock signal is applied directly to the non-inverting input of an AB gate. The output of the AB gate and an external enabling signal are provided to first and second inputs of a NOR gate the output of which represents the internal enabling signal which is fed back to the inverting input of the AB gate. Thus, the clock signal propagates through only two stages of delay rather than three as is the case with prior art enabling circuitry.