Abstract: A digital system and method of operation is provided in which several processors (440, 450) are connected to a shared memory resource (460). Translation lookaside buffers (TLB) (400, 402) are connected to receive a request address (404a-n) from each respective processor. Each TLB has a set of entries that correspond to pages of address space. Each entry provides a set of task memory attributes (TMA) (412a-n) for the associated page of address space. Task memory attributes are defined by a task control block associated with a currently executing task. For each memory transfer request, the TLB accesses an entry corresponding to the request address and provides a translated physical memory address and a task memory attribute value associated with that requested address space page. Functional circuitry (470) performs pre/post-processing on data that is being transferred between a processor and the memory in accordance with the task memory attribute value provided by the TLB with each memory transfer request.

Abstract: A digital system and method of operation is provided in which several processors (440, 450) are connected to a shared memory resource (460). Translation lookaside buffers (TLB) (400, 402) are connected to receive a request address (404a-n) from each respective processor. Each TLB has a set of entries that correspond to pages of address space. Each entry provides a set of task memory attributes (TMA) (412a-n) for the associated page of address space. Task memory attributes are defined by a task control block associated with a currently executing task. For each memory transfer request, the TLB accesses an entry corresponding to the request address and provides a translated physical memory address and a task memory attribute value associated with that requested address space page. Functional circuitry (470) performs pre/post-processing on data that is being transferred between a processor and the memory in accordance with the task memory attribute value provided by the TLB with each memory transfer request.

Abstract: Generally, in one form of the invention, a computer system for executing application programs in hard real-time, comprises a central processing unit (CPU) for executing the application programs and system programs and a computer memory partitioned into a data memory and a code memory. A garbage collector, which executes on said CPU, places a write barrier over certain portions of memory. Furthermore, it transfers an object from a location in the memory to a second object at another location in the memory. In a critical section, which may not be interrupted, it allocates sufficient space for the second object so that the entire contents from the first object can be copied into the second object, and in an interruptable section, it copies the entire contents of the first object into the second object. A write routine is linked into the application programs for updating objects in the computer memory.

Abstract: A task scheduling method for a real time computer system having automatic memory management or some other resource that is consumed in terms of a bit rate. The method ensures that non critical tasks do not prevent the timely execution of critical tasks. Each task is evaluated in terms of its rate of consumption of the resource. This rate is controlled by assigning each task a consumption quota and keeping track of the consumption of each task as it executes. The task is required to relinquish its processor time if it attempts to consume more than its quota.